[Intel-gfx] [PATCH 05/11] drm/i915: remove rps local variables
Ben Widawsky
benjamin.widawsky at intel.com
Tue Feb 18 04:01:46 CET 2014
With the renamed RPS struct members, it's easier to skip the local
variables which no longer clarify anything, and if anything just make
the code harder to read.
The real motivation for this patch is actually the next patch, which
attempts to consolidate some of the functionality.
Cc: Jeff McGee <jeff.mcgee at intel.com>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
drivers/gpu/drm/i915/i915_sysfs.c | 37 ++++++++++++-------------------------
drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++--------------
2 files changed, 27 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 27cf344..6f83cca 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -313,7 +313,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
struct drm_minor *minor = dev_to_drm_minor(kdev);
struct drm_device *dev = minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 val, hw_max, hw_min, non_oc_max;
+ u32 val;
ssize_t ret;
ret = kstrtou32(buf, 0, &val);
@@ -324,27 +324,19 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev_priv->dev)) {
+ if (IS_VALLEYVIEW(dev_priv->dev))
val = vlv_freq_opcode(dev_priv, val);
-
- hw_max = dev_priv->rps.max_freq_hardlimit;
- hw_min = dev_priv->rps.min_freq_hardlimit;
- non_oc_max = hw_max;
- } else {
+ else
val /= GT_FREQUENCY_MULTIPLIER;
- hw_max = dev_priv->rps.max_freq_overclock;
- non_oc_max = dev_priv->rps.max_freq_hardlimit;
- hw_min = dev_priv->rps.min_freq_hardlimit;
- }
-
- if (val < hw_min || val > hw_max ||
+ if (val < dev_priv->rps.min_freq_hardlimit ||
+ val > dev_priv->rps.max_freq_overclock ||
val < dev_priv->rps.min_freq_softlimit) {
mutex_unlock(&dev_priv->rps.hw_lock);
return -EINVAL;
}
- if (val > non_oc_max)
+ if (val > dev_priv->rps.max_freq_hardlimit)
DRM_DEBUG("User requested overclocking to %d\n",
val * GT_FREQUENCY_MULTIPLIER);
@@ -393,7 +385,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
struct drm_minor *minor = dev_to_drm_minor(kdev);
struct drm_device *dev = minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 val, hw_max, hw_min;
+ u32 val;
ssize_t ret;
ret = kstrtou32(buf, 0, &val);
@@ -404,19 +396,14 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
mutex_lock(&dev_priv->rps.hw_lock);
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev))
val = vlv_freq_opcode(dev_priv, val);
-
- hw_max = dev_priv->rps.max_freq_hardlimit;
- hw_min = dev_priv->rps.min_freq_hardlimit;
- } else {
+ else
val /= GT_FREQUENCY_MULTIPLIER;
- hw_max = dev_priv->rps.max_freq_overclock;
- hw_min = dev_priv->rps.min_freq_hardlimit;
- }
-
- if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
+ if (val < dev_priv->rps.min_freq_hardlimit ||
+ val > dev_priv->rps.max_freq_overclock ||
+ val > dev_priv->rps.max_freq_softlimit) {
mutex_unlock(&dev_priv->rps.hw_lock);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 341c154..e63515a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3321,7 +3321,7 @@ static void gen6_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
- u32 rp_state_cap, hw_max, hw_min;
+ u32 rp_state_cap;
u32 gt_perf_status;
u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
u32 gtfifodbg;
@@ -3350,19 +3350,19 @@ static void gen6_enable_rps(struct drm_device *dev)
gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
/* In units of 50MHz */
- dev_priv->rps.max_freq_overclock = hw_max = rp_state_cap & 0xff;
- hw_min = (rp_state_cap >> 16) & 0xff;
+ dev_priv->rps.nominal_freq = (rp_state_cap >> 16) & 0xff;
dev_priv->rps.min_freq_hardlimit = (rp_state_cap >> 8) & 0xff;
dev_priv->rps.max_freq_hardlimit = (rp_state_cap >> 0) & 0xff;
+ dev_priv->rps.max_freq_overclock = dev_priv->rps.max_freq_hardlimit;
dev_priv->rps.nominal_freq = dev_priv->rps.min_freq_hardlimit;
dev_priv->rps.cur_freq = 0;
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
- dev_priv->rps.max_freq_softlimit = hw_max;
+ dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq_hardlimit;
if (dev_priv->rps.min_freq_softlimit == 0)
- dev_priv->rps.min_freq_softlimit = hw_min;
+ dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq_hardlimit;
/* disable the counters and set deterministic thresholds */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -3590,7 +3590,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring;
- u32 gtfifodbg, val, hw_max, hw_min, rc6_mode = 0;
+ u32 gtfifodbg, val, rc6_mode = 0;
int i;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -3652,27 +3652,28 @@ static void valleyview_enable_rps(struct drm_device *dev)
vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
dev_priv->rps.cur_freq);
- dev_priv->rps.max_freq_overclock = hw_max = valleyview_rps_max_freq(dev_priv);
+ dev_priv->rps.max_freq_hardlimit = valleyview_rps_max_freq(dev_priv);
+ dev_priv->rps.max_freq_overclock = dev_priv->rps.max_freq_hardlimit;
DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
- vlv_gpu_freq(dev_priv, hw_max),
- hw_max);
+ vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_hardlimit),
+ dev_priv->rps.max_freq_hardlimit);
dev_priv->rps.nominal_freq = valleyview_rps_rpe_freq(dev_priv);
DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
vlv_gpu_freq(dev_priv, dev_priv->rps.nominal_freq),
dev_priv->rps.nominal_freq);
- hw_min = valleyview_rps_min_freq(dev_priv);
+ dev_priv->rps.min_freq_hardlimit = valleyview_rps_min_freq(dev_priv);
DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
- vlv_gpu_freq(dev_priv, hw_min),
- hw_min);
+ vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_hardlimit),
+ dev_priv->rps.min_freq_hardlimit);
/* Preserve min/max settings in case of re-init */
if (dev_priv->rps.max_freq_softlimit == 0)
- dev_priv->rps.max_freq_softlimit = hw_max;
+ dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq_hardlimit;
if (dev_priv->rps.min_freq_softlimit == 0)
- dev_priv->rps.min_freq_softlimit = hw_min;
+ dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq_hardlimit;
DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
vlv_gpu_freq(dev_priv, dev_priv->rps.nominal_freq),
--
1.8.5.5
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