[Intel-gfx] [PATCH 1/5] drm/i915: Fix forcewake counts for gen8

[Ben Widawsky]

On Mon, Feb 24, 2014 at 01:27:09PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 21, 2014 at 11:38:48AM -0800, Ben Widawsky wrote:
> > On Fri, Feb 21, 2014 at 05:31:59PM +0200, mika.kuoppala at intel.com wrote:
> > > From: Mika Kuoppala <mika.kuoppala at intel.com>
> > > 
> > > Sometimes generic driver code gets forcewake explicitly by
> > > gen6_gt_force_wake_get(), which check forcewake_count before accessing
> > > hardware. However the register access with gen8_write function access
> > > low level hw accessors directly, ignoring the forcewake_count. This
> > > leads to nested forcewake get from hardware, in ring init and possibly
> > > elsewhere, causing forcewake ack clear errors and/or hangs.
> > > 
> > > Fix this by checking the forcewake count also in gen8_write
> > > 
> > > v2: Read side doesn't care about shadowed registers,
> > >     Remove __needs_put funkiness from gen8_write. (Ville)
> > >     Improved commit message.
> > > 
> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=74007
> > > Cc: Ben Widawsky <benjamin.widawsky at intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
> > > Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
> > 
> > For those concerned with the performance implication of the extra if
> > (if anyone at all cares, it's Chris) - I suppose we could also just add
> > the lock to gen6_gt_force_wake_get/put.
> 
> Two things:
> a) I don't understand what you mean here. uncore.lock already protects
> the forcewake count in gen6_gt_force_wake_get/put. Also there's no way
> to avoid the branch here since doing a .force_wake_put() w/o checking
> the forcewake count is never ok.
> 

I meant acquire the lock in get() release the lock in put()

> b) The cost of branch should be a drop in the ocean compared to the
> cost of the register reads/writes in .forcewake_get/put.
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Ben Widawsky, Intel Open Source Technology Center