[Intel-gfx] [PATCH v4 5/5] drm/tegra: Add eDP support

[Thierry Reding]

On Wed, Jan 22, 2014 at 02:14:07PM -0700, Stephen Warren wrote:
> On 01/21/2014 12:24 PM, Thierry Reding wrote:
[...]
> > +static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
> 
> Is that anything like writesl(); similar for
> tegra_dpaux_read_fifo()/readsl()?

I never got around to replying to this: the interface to the DPAUX FIFO
isn't a single register that uses non-incrementing writes, but rather a
set of five registers that map the entire FIFO linearly. So it can't be
written to with writesl() or read from with readsl().

The function names are slightly confusing in this regard. But the write
destination is still a FIFO, hence this choice of name.

Thierry
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