[Intel-gfx] [PATCH 2/5] drm/i915: Change intel_fdi_link_freq() to 10kHz

Paulo Zanoni przanoni at gmail.com
Fri Feb 28 23:28:41 CET 2014


2014-02-27 9:23 GMT-03:00  <ville.syrjala at linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> We normally use 10Khz units when describing DP link frequency.
> Have intel_fdi_link_freq() return the same units. I always get confused
> when the units start to be totally different.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

A nice simplification!

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 17 +++++------------
>  1 file changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f19e6ea..a366e91 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -81,14 +81,14 @@ intel_pch_rawclk(struct drm_device *dev)
>         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
>  }
>
> -static inline u32 /* units of 100MHz */
> +static inline int /* units of 10kHz */
>  intel_fdi_link_freq(struct drm_device *dev)
>  {
>         if (IS_GEN5(dev)) {
>                 struct drm_i915_private *dev_priv = dev->dev_private;
> -               return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
> +               return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
>         } else
> -               return 27;
> +               return 270000;
>  }
>
>  static const intel_limit_t intel_limits_i8xx_dac = {
> @@ -4521,14 +4521,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
>         bool setup_ok, needs_recompute = false;
>
>  retry:
> -       /* FDI is a binary signal running at ~2.7GHz, encoding
> -        * each output octet as 10 bits. The actual frequency
> -        * is stored as a divider into a 100MHz clock, and the
> -        * mode pixel clock is stored in units of 1KHz.
> -        * Hence the bw of each lane in terms of the mode signal
> -        * is:
> -        */
> -       link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
> +       link_bw = intel_fdi_link_freq(dev);
>
>         fdi_dotclock = adjusted_mode->crtc_clock;
>
> @@ -8069,7 +8062,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
>          * get_config() function.
>          */
>         pipe_config->adjusted_mode.crtc_clock =
> -               intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
> +               intel_dotclock_calculate(intel_fdi_link_freq(dev),
>                                          &pipe_config->fdi_m_n);
>  }
>
> --
> 1.8.3.2
>
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-- 
Paulo Zanoni



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