[Intel-gfx] [PATCH 2/3] drm/i915: Enable watermarks for BDW

ville.syrjala at linux.intel.com ville.syrjala at linux.intel.com
Tue Jan 7 15:14:09 CET 2014


From: Ville Syrjälä <ville.syrjala at linux.intel.com>

We forgot to intialize the watermark vfuncs for BDW, and hence the
watermarks were never updated.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5637183..04e1e29 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5628,6 +5628,17 @@ void intel_init_pm(struct drm_device *dev)
 			}
 			dev_priv->display.init_clock_gating = haswell_init_clock_gating;
 		} else if (INTEL_INFO(dev)->gen == 8) {
+			if (dev_priv->wm.pri_latency[0] &&
+			    dev_priv->wm.spr_latency[0] &&
+			    dev_priv->wm.cur_latency[0]) {
+				dev_priv->display.update_wm = ilk_update_wm;
+				dev_priv->display.update_sprite_wm =
+					ilk_update_sprite_wm;
+			} else {
+				DRM_DEBUG_KMS("Failed to read display plane latency. "
+					      "Disable CxSR\n");
+				dev_priv->display.update_wm = NULL;
+			}
 			dev_priv->display.init_clock_gating = gen8_init_clock_gating;
 		} else
 			dev_priv->display.update_wm = NULL;
-- 
1.8.3.2




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