[Intel-gfx] [PATCH] drm/i915: fix fastboot pfit disable hack to update pipe w/h

[Daniel Vetter]

On Tue, Jan 7, 2014 at 7:52 PM, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
>> >> index 4d1357a..7e46d75 100644
>> >> --- a/drivers/gpu/drm/i915/intel_display.c
>> >> +++ b/drivers/gpu/drm/i915/intel_display.c
>> >> @@ -2382,6 +2382,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
>> >>                       I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
>> >>                       I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
>> >>               }
>> >> +             intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
>> >> +             intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
>> >>       }
>> >>
>> >>       ret = dev_priv->display.update_plane(crtc, fb, x, y);
>> >
>> > References: https://bugzilla.kernel.org/show_bug.cgi?id=67591
>>
>> The bug report doesn't say anything about the pipe config state
>> checker being unhappy. Are we missing a call to the checker for
>> fastboot somewhere to catch this stuff?
>
> Ah no, we do have a check there.  I guess since we never updated it we
> were comparing two stale values?

The hw values should reflect what we're writing into the PF_WIN_*
registers, but the sw side should be stale. I think a dpms on/off
should trigger a checker warning, but having one after each
fastboot'ed setCrtc might be benefitial in general. I just want to
make sure that we don't have more dragons lurking ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch