[Intel-gfx] [PATCH] drm/i915/vlv: Added/removed Render specific Hw Workarounds for VLV

[Ville Syrjälä]

On Thu, Jan 09, 2014 at 05:21:49PM +0530, akash.goel at intel.com wrote:
> From: akashgoe <akash.goel at intel.com>
> 
> The following changes leads to stable behavior, especially
> when playing 3D Apps, benchmarks.
> 
> Added 4 new rendering specific Workarounds
> 1. WaTlbInvalidateStoreDataBefore :-
>      Before pipecontrol with TLB invalidate set,
>      need 2 store data commands
> 2. WaReadAfterWriteHazard :-
>      Send 8 store dword commands after flush
>      for read after write hazard
>      (HSD Gen6 bug_de 3047871)
> 3. WaVSThreadDispatchOverride
>      Performance optimization - Hw will
>      decide which half slice the thread
>      will dispatch, May not be really needed
>      for VLV, as its single slice
> 4. WaDisable_RenderCache_OperationalFlush
>      Operational flush cannot be enabled on
>      BWG A0 [Errata BWT006]
> 
> Removed 3 workarounds as not needed for VLV+(B0 onwards)
> 1. WaDisableRHWOOptimizationForRenderHang
> 2. WaDisableL3CacheAging
> 3. WaDisableDopClockGating
> 
> Modified the implementation of 1 workaround
> 1. WaDisableL3Bank2xClockGate
>     Disabling L3 clock gating- MMIO 940c[25] = 1
> 
> Modified the programming of 2 registers in render ring init function
> 1. GFX_MODE_GEN7 (Enabling TLB invalidate)
> 2. MI_MODE (Enabling MI Flush)

I posted a bunch of workaround stuff a long time ago. It may have some
overlaps with your stuff, and maybe there was something you overlooked.
Maybe you could have a look if there's something useful there:
http://lists.freedesktop.org/archives/intel-gfx/2013-July/029685.html

-- 
Ville Syrjälä
Intel OTC