[Intel-gfx] [PATCH v4 1/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

[S, Deepak]

>At this point we've not yet computed the final new_delay. It would seem better to me to put all this code to place where we have the final new_delay.

I agree we can add this after we have the final new_delay.  We can add this in two places one in gen6_pm_rps_work before we call valleyview_set_rps or add this inside valleyview_set_rps
Since the changes are specific to vlv. I think it is better to add it within valleyview_set_rps before requesting the freq. Thoughts?

>Also I wonder if we should also mask the DOWN_TIMEOUT interrupt?
I think we need to do unmasking of DOWN_TIMEOUT, Idea, here is when we hit the max_dealy we mask the UP_TIMEOUT and umask the DOWN_TIMEOUT and viceversa to make sure we enable the interrupts based on whether we are going up or down and avoid the interrupts that are not required..

-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrjala at linux.intel.com] 
Sent: Tuesday, January 21, 2014 8:05 PM
To: S, Deepak
Cc: intel-gfx at lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Disable/Enable PM Intrrupts based on the current freq.

On Mon, Jan 20, 2014 at 06:40:24PM +0530, deepak.s at intel.com wrote:
> From: Deepak S <deepak.s at intel.com>
> 
> When current delay is already at max delay, Let's disable the PM UP 
> THRESHOLD INTRRUPTS, so that we will not get further interrupts until 
> current delay is less than max delay, Also request for the PM DOWN 
> THRESHOLD INTRRUPTS to indicate the decrease in clock freq. and 
> viceversa for PM DOWN THRESHOLD INTRRUPTS.
> 
> v2: Use bool variables (Daniel)
> 
> v3: Fix Interrupt masking bit (Deepak)
> 
> v4: Use existing symbolic constants in i915_reg.h (Daniel)
> 
> Signed-off-by: Deepak S <deepak.s at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  3 +++  
> drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++++++--  
> drivers/gpu/drm/i915/intel_pm.c |  3 +++
>  3 files changed, 35 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> b/drivers/gpu/drm/i915/i915_drv.h index f888fea..e89b9f4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -943,6 +943,9 @@ struct intel_gen6_power_mgmt {
>  	u8 rp0_delay;
>  	u8 hw_max;
>  
> +	bool rp_up_masked;
> +	bool rp_down_masked;
> +
>  	int last_adj;
>  	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c 
> b/drivers/gpu/drm/i915/i915_irq.c index 160d65d..d0d87ed 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -993,7 +993,20 @@ static void gen6_pm_rps_work(struct work_struct *work)
>  			adj *= 2;
>  		else
>  			adj = 1;
> -		new_delay = dev_priv->rps.cur_delay + adj;
> +
> +		if (dev_priv->rps.cur_delay >= dev_priv->rps.max_delay) {
> +			I915_WRITE(GEN6_PMINTRMSK,
> +					I915_READ(GEN6_PMINTRMSK) |  GEN6_PM_RP_UP_THRESHOLD);
> +			dev_priv->rps.rp_up_masked = true;
> +			new_delay = dev_priv->rps.cur_delay;
> +		} else
> +			new_delay = dev_priv->rps.cur_delay + adj;
> +
> +		if (dev_priv->rps.rp_down_masked) {
> +			I915_WRITE(GEN6_PMINTRMSK,
> +					I915_READ(GEN6_PMINTRMSK) & ~GEN6_PM_RP_DOWN_THRESHOLD);
> +			dev_priv->rps.rp_down_masked = false;
> +		}

At this point we've not yet computed the final new_delay. It would seem better to me to put all this code to place where we have the final new_delay.

Also I wonder if we should also mask the DOWN_TIMEOUT interrupt?

>  
>  		/*
>  		 * For better performance, jump directly @@ -1012,7 +1025,21 @@ 
> static void gen6_pm_rps_work(struct work_struct *work)
>  			adj *= 2;
>  		else
>  			adj = -1;
> -		new_delay = dev_priv->rps.cur_delay + adj;
> +
> +		if (dev_priv->rps.cur_delay <= dev_priv->rps.min_delay) {
> +			I915_WRITE(GEN6_PMINTRMSK,
> +					I915_READ(GEN6_PMINTRMSK) | GEN6_PM_RP_DOWN_THRESHOLD);
> +			dev_priv->rps.rp_down_masked = true;
> +			new_delay = dev_priv->rps.cur_delay;
> +		} else
> +			new_delay = dev_priv->rps.cur_delay + adj;
> +
> +		if (dev_priv->rps.rp_up_masked) {
> +			I915_WRITE(GEN6_PMINTRMSK,
> +					I915_READ(GEN6_PMINTRMSK) & ~GEN6_PM_RP_UP_THRESHOLD);
> +			dev_priv->rps.rp_up_masked = false;
> +		}

Same comments apply.

> +
>  	} else { /* unknown event */
>  		new_delay = dev_priv->rps.cur_delay;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> b/drivers/gpu/drm/i915/intel_pm.c index b9b4fe4..d00a2cf 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3613,6 +3613,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
>  			 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
>  			 dev_priv->rps.rpe_delay);
>  
> +	dev_priv->rps.rp_up_masked = false;
> +	dev_priv->rps.rp_down_masked = false;
> +
>  	valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
>  
>  	gen6_enable_rps_interrupts(dev);
> --
> 1.8.4.2
> 
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--
Ville Syrjälä
Intel OTC