[Intel-gfx] [PATCH] drm/i915: GEN7_MSG_CONTROL is ivb-only

[Runyan, Arthur J]

The equivalent function moved to register NDE_RSTWRN_OPT bit 4 "RST PCH Handshake En" on Haswell.  You'll need to convert the WAIT_FOR_PCH_*_ACK  programming over to that new location.  

>-----Original Message-----
>From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch]
>Sent: Wednesday, January 22, 2014 12:57 AM
>To: Intel Graphics Development
>Cc: Daniel Vetter; Runyan, Arthur J; Dave Airlie
>Subject: [PATCH] drm/i915: GEN7_MSG_CONTROL is ivb-only
>
>At least I couldn't find it in the Haswell Bspec any more and we've
>tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
>hit the PCH_NOP path) and the unclaimed register logic complained.
>
>So restrict this dance to just ivb platforms.
>
>Cc: Arthur Ranyan <arthur.j.runyan at intel.com>
>Cc: Dave Airlie <airlied at gmail.com>
>Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
>---
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>index 32636a470367..13a5003b320a 100644
>--- a/drivers/gpu/drm/i915/i915_gem.c
>+++ b/drivers/gpu/drm/i915/i915_gem.c
>@@ -4495,7 +4495,7 @@ i915_gem_init_hw(struct drm_device *dev)
> 		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
> 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
>-	if (HAS_PCH_NOP(dev)) {
>+	if (HAS_PCH_NOP(dev) && IS_IVYBRIDGE(dev)) {
> 		u32 temp = I915_READ(GEN7_MSG_CTL);
> 		temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> 		I915_WRITE(GEN7_MSG_CTL, temp);
>--
>1.8.5.2