[Intel-gfx] [PATCH 00/10] drm/i915: Some less complex FBC fixes

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Since fixing the FBC locking is a bigger task that will take a while,
I decided to pull all the simple fixes from my branch and post them
right away.

Some of these I've posted before, some others have seen a bit of action
by being in a public branch.

The FBC_FENCE_OFF change is just a guess at this point. The odd offset
just caught my eye while reading throguh i915_reg.h.

Ville Syrjälä (10):
  drm/i915: Don't write IVB_FBC_RT_BASE
  drm/i915: Don't set persistent FBC mode on ILK/SNB
  drm/i915: Don't set DPFC_HT_MODIFY bit on CTG/ILK/SNB
  drm/i915: Improve FBC plane defines a bit
  drm/i915: Use 1/2 compression ratio limit for 16bpp on FBC2
  drm/i915: Actually write the correct bits to DPFC_CONTROL on CTG
  drm/i915: Don't preserve DPFC_CONTROL bits ILK/SNB
  drm/i915: Kill most of the FBC register save/restore
  drm/i915: Fix FBC1 enable message
  drm/i915: Fix FBC_FENCE_OFF

 drivers/gpu/drm/i915/i915_drv.h     |  4 ----
 drivers/gpu/drm/i915/i915_reg.h     | 10 ++++-----
 drivers/gpu/drm/i915/i915_suspend.c | 32 +++++++----------------------
 drivers/gpu/drm/i915/intel_pm.c     | 41 ++++++++++++++++++++-----------------
 4 files changed, 33 insertions(+), 54 deletions(-)

-- 
1.8.3.2