[Intel-gfx] [PATCH] drm/i915: enable HiZ Raw Stall Optimization

[Chia-I Wu]

[Additional comments, and copy Ian and Chad for real]

On Mon, Jan 27, 2014 at 4:18 PM, Chia-I Wu <olvaffe at gmail.com> wrote:
> From: Chia-I Wu <olv at lunarg.com>
>
> The optimization is available on Ivy Bridge and later, and is disabled by
> default.  Enabling it helps certain workloads such as GLBenchmark TRex test.
With the patch applied, GLB27_TRex_C24Z16_FixedTimeStep goes from
99fps to 109fps on my Haswell, and from 60fps to 65fps on my Ivy
Bridge.  No piglit regression on both GENs.

I had a non-recoverable system hang once with the patch applied.  I
was not sure if it is because of the patch or drm-intel-nightly (which
I checkout out some weeks ago).  I did my tests today against latest
drm-intel-next, and did not have any hang.  Since the optimization is
disabled by default, I am curious if there is any caveat before
enabling it.

>
> Signed-off-by: Chia-I Wu <olv at lunarg.com>
> Cc: Ian Romanick <ian.d.romanick at intel.com>
> Cc: Chad Versace <chad.versace at linux.intel.com>
>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     | 2 ++
>  drivers/gpu/drm/i915/i915_suspend.c | 9 +++++++--
>  drivers/gpu/drm/i915/intel_pm.c     | 8 ++++++++
>  3 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ee27421..bd90ef3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -930,6 +930,8 @@
>  #define   ECO_GATING_CX_ONLY   (1<<3)
>  #define   ECO_FLIP_DONE                (1<<0)
>
> +#define CACHE_MODE_0_GEN7      0x7000 /* IVB+ */
> +#define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
>  #define CACHE_MODE_1           0x7004 /* IVB+ */
>  #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
>
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 98790c7..13fefbd 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev)
>         intel_disable_gt_powersave(dev);
>
>         /* Cache mode state */
> -       if (INTEL_INFO(dev)->gen < 7)
> +       if (INTEL_INFO(dev)->gen >= 7)
> +               dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7);
> +       else
>                 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
>
>         /* Memory Arbitration state */
> @@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev)
>         }
>
>         /* Cache mode state */
> -       if (INTEL_INFO(dev)->gen < 7)
> +       if (INTEL_INFO(dev)->gen >= 7)
> +               I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 |
> +                          0xffff0000);
> +       else
>                 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
>                            0xffff0000);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 26c29c1..d6ddc39 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>         /* WaVSRefCountFullforceMissDisable:hsw */
>         gen7_setup_fixed_func_scheduler(dev_priv);
>
> +       /* enable HiZ Raw Stall Optimization */
> +       I915_WRITE(CACHE_MODE_0_GEN7,
> +                  _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> +
>         /* WaDisable4x2SubspanOptimization:hsw */
>         I915_WRITE(CACHE_MODE_1,
>                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> @@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>         /* WaVSRefCountFullforceMissDisable:ivb */
>         gen7_setup_fixed_func_scheduler(dev_priv);
>
> +       /* enable HiZ Raw Stall Optimization */
> +       I915_WRITE(CACHE_MODE_0_GEN7,
> +                  _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> +
>         /* WaDisable4x2SubspanOptimization:ivb */
>         I915_WRITE(CACHE_MODE_1,
>                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
> --
> 1.8.5.3
>



-- 
olv at LunarG.com