[Intel-gfx] [PATCH 1/5] drm/i915: Implement CS stall workaround on Broadwell.

[Kenneth Graunke]

According to the latest documentation, any PIPE_CONTROL with the
"Command Streamer Stall" bit set must also have another bit set,
with five different options.  I chose "Stall at Pixel Scoreboard"
since we've used it effectively in the past, but the choice is
fairly arbitrary.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e75d8b3..313b1bd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -370,7 +370,14 @@ gen8_render_ring_flush(struct intel_ring_buffer *ring,
 	u32 scratch_addr = ring->scratch.gtt_offset + 128;
 	int ret;
 
-	flags |= PIPE_CONTROL_CS_STALL;
+	/* For CS stalls, one of the following must also be set:
+	 * - Render Target Cache Flush
+	 * - Depth Cache Flush
+	 * - Stall at Pixel Scoreboard
+	 * - Post-Sync Operation
+	 * We arbitrarily choose "Stall at Scoreboard".
+	 */
+	flags |= PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
-- 
1.8.5.2