[Intel-gfx] [PATCH 20/28] drm/i915: Drop WaDisableRCPBUnitClockGating:vlv

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>

On Wed, Jan 22, 2014 at 5:32 PM,  <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Only early VLV steppings needed thist. Should no longer be relevant.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 14 +++-----------
>  1 file changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0d9ded4..593046a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4927,24 +4927,16 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
>                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> -       /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> -        * gating disable must be set.  Failure to set it results in
> -        * flickering pixels due to Z write ordering failures after
> -        * some amount of runtime in the Mesa "fire" demo, and Unigine
> -        * Sanctuary and Tropics, and apparently anything else with
> -        * alpha test or pixel discard.
> -        *
> +       /*
>          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
>          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
>          *
> -        * Also apply WaDisableVDSUnitClockGating:vlv and
> -        * WaDisableRCPBUnitClockGating:vlv.
> +        * Also apply WaDisableVDSUnitClockGating:vlv.
>          */
>         I915_WRITE(GEN6_UCGCTL2,
>                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
>                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
> -                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
> -                  GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
> +                  GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
>         /* WaDisableL3Bank2xClockGate:vlv */
>         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> --
> 1.8.3.2
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br