[Intel-gfx] [PATCH 18/28] drm/i915: Drop WaDisableRCZUnitClockGating:hsw

[Daniel Vetter]

On Wed, Jan 22, 2014 at 09:32:54PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> WaDisableRCZUnitClockGating was needed with early HSW steppings only.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

I couldn't make sense of this diff, my hsw clock_gating function here
doesn't seem to have this hunk?!
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bf45b4c..70f3b2b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4762,11 +4762,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  
>  	ilk_init_lp_watermarks(dev);
>  
> -	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> -	 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
> -	 */
> -	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> -
>  	/* WaApplyL3ControlAndL3ChickenMode:hsw */
>  	I915_WRITE(GEN7_L3CNTLREG1,
>  			GEN7_WA_FOR_GEN7_L3_CONTROL);
> -- 
> 1.8.3.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch