[Intel-gfx] [PATCH v2 2/2] drm/i915: fix initial timestamps for PP sequencing logic

[Chris Wilson]

On Wed, Jan 29, 2014 at 01:25:41PM +0200, Imre Deak wrote:
> The initial jiffies value can be non-0, so set the inital panel power
> sequencer timestamps accordingly. This didn't cause a problem on 64 bit
> machines but on 32 bit jiffies is initially -300*HZ, so if the panel
> power is initally off in the call from edp_panel_vdd_on()->
> wait_panel_power_cycle() we'd wait up to ~300 sec more than needed.
> 
> Signed-off-by: Imre Deak <imre.deak at intel.com>

I would have set them all to the same value personally, but
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre