[Intel-gfx] [PATCH 06/13] drm/i915/bdw: implement semaphore signal

[Daniel Vetter]

On Thu, Jan 30, 2014 at 1:46 PM, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> Oh. So they changed how post-sync writes operated - this should be a
> separate fix for stable I believe (so that batches are not run before we
> have finished invalidating the TLBs required).

We have an igt to exercise tlb invalidation stuff, which runs on all
rings. But it only runs a batch, so only uses the CS tlb. Do we need
to extend this?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch