[Intel-gfx] [PATCH 1/2] drm/i915/gen8: Invalidate TLBs before PDP reload

[Chris Wilson]

On Thu, Jul 03, 2014 at 03:01:49PM -0700, Ben Widawsky wrote:
> This is a spec requirement for all rings.
> 
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 5b4a9a0..1ac648f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -870,6 +870,9 @@ int i915_switch_context(struct intel_engine_cs *ring,
>  	if (from == to && !to->remap_slice)
>  		return 0;
>  
> +	if (IS_GEN8(ring->dev))
> +		WARN_ON(ring->flush(ring, I915_GEM_GPU_DOMAINS, 0));
> +

That's intel_ring_invalidate_all_caches(). The only time we won't be
doing this are the forced switches at startup/reset and close. Is the
requirement before or after the SET_CONTEXT? What I would prefer doing
is moving the invalidate-dispatch-flush-signal into one atomic operation
(that would help simplify execlist as well) - would that be good enough
here to be sure that an invalidate is performed after the context
switch and before the next batch?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre