[Intel-gfx] [PATCH 2/5] drm/i915: preserve swizzle settings if necessary v3
Daniel Vetter
daniel at ffwll.ch
Mon Jul 7 11:03:41 CEST 2014
On Fri, Jun 27, 2014 at 09:15:25AM -0700, Steve Aarnio wrote:
> On 06/11/2014 08:41 AM, Jesse Barnes wrote:
> >On Wed, 11 Jun 2014 17:39:29 +0200
> >Daniel Vetter <daniel at ffwll.ch> wrote:
> >
> >>On Wed, Jun 11, 2014 at 5:13 PM, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> >>>>- If you have a machine which uses tiled framebuffers and enables
> >>>> swizzling in the BIOS your code will a) drop the swizzle setup in
> >>>> gem_init_hw, breaking resume b) not set the swizzle settings correctly
> >>>> in swizzle_detect, breaking swap in/out and pwrite/pread. Not sure such
> >>>> a machine exists, but still.
> >>>
> >>>This would affect krh's MBA, which is why I wanted testing here...
> >>>anyway I'll spin a new one and ask krh to test again.
> >>
> >>Hm, I've thought the issue with the MBA is that it used tiled fbs, but
> >>non-swizzled. And then a mess ensued when we've enabled it. But yeah,
> >>unfortunately with the new logic we need to retest :(
> >
> >Ah yeah I think you're right, either way, need more testing.
> >
> >Maybe we should have just gone with the first patch to never enable
> >swizzling based on Art's assertion that it didn't matter.
> >
>
> I hate to jump into the middle of a conversation that may or may not be
> related to a patch I just posted... but...
>
> There was a very long internal discussion that the Windows guys had with
> H/W. For Gen8+ H/W recommends disabling CSX swizzle. Technically, BDW still
> supports it, but there is a bug _somewhere_ that makes it problematic. In
> any case it goes away for sure with Gen9+, so disabling on Gen8 doesn't
> hurt.
>
> According to the other discussion, the H/W guys say that enabling actually
> hurts performance slightly, and the driver should leave the swizzle
> decisions to the memory controller.
Patch to disable swizzling detection on gen8+ in i915_gem_tiling.c (only
there, imo ok to keep the hw paths around for setting up the registers)
welcome ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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