[Intel-gfx] [PATCH 01/40] drm/i915: Try to populate mem_freq for chv

[Deepak S]

On Saturday 28 June 2014 04:33 AM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> mem_freq is needed to decode the GPU freq opcodes.
>
> FIXME: Punit reg seems to contain garbage so this isn't right
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 07c040c..ef00756 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5629,6 +5629,24 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>   static void cherryview_init_clock_gating(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> +	mutex_unlock(&dev_priv->rps.hw_lock);
> +	switch ((val >> 6) & 3) {
> +	case 0:
> +	case 1:
> +		dev_priv->mem_freq = 800;
> +		break;
> +	case 2:
> +		dev_priv->mem_freq = 1066;
> +		break;
> +	case 3:
> +		dev_priv->mem_freq = 1333;
> +		break;
> +	}
> +	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>   
>   	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>   

Added the right way of getting the mem_freq for CHV

*http://lists.freedesktop.org/archives/intel-gfx/2014-July/048897.html*

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