[Intel-gfx] [PATCH 5/8] drm/i915: Add WaHdcDisableFetchWhenMasked:bdw

[Michel Thierry]

Set desired default value for HDCCHICKEN register for BDW platform.

Signed-off-by: Michel Thierry <michel.thierry at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aaadf4a..55ea3bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4702,6 +4702,7 @@ enum punit_power_well {
 /* GEN8 chicken */
 #define HDC_CHICKEN0				0x7300
 #define  HDC_FENCE_DESTINATION_TO_SLM_DISABLE	(1<<14)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED		(1<<11)
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
 
 /* WaProgramL3SqcReg1Default */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8bde0aa..b60fbd2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5450,10 +5450,12 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	 * workaround for for a possible hang in the unlikely event a TLB
 	 * invalidation occurs during a PSD flush.
 	 * WaDisableFenceDestinationToSLM:bdw
+	 * WaHdcDisableFetchWhenMasked:bdw
 	 */
 	I915_WRITE(HDC_CHICKEN0,
 		   I915_READ(HDC_CHICKEN0) |
 		   _MASKED_BIT_ENABLE(HDC_FENCE_DESTINATION_TO_SLM_DISABLE) |
+		   _MASKED_BIT_ENABLE(HDC_DONOT_FETCH_MEM_WHEN_MASKED) |
 		   _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
 
 	/* WaVSRefCountFullforceMissDisable:bdw */
-- 
1.9.0