[Intel-gfx] [PATCH 04/11] CHROMIUM: drm/i915/vlv: Initialize pipe B backlight to A's value

[clinton.a.taylor at intel.com]

From: Ben Widawsky <benjamin.widawsky at intel.com>

Not sure if this is needed or not. The code still falls back to a
potentially bad value if PIPE_A was not set.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Signed-off-by: Wayne Boyer <wayne.boyer at intel.com>

Change-Id: I54eb5d4d9fd93e86878c9fa1daec19bdb6b3bd0b
Reviewed-on: https://chromium-review.googlesource.com/196605
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Tested-by: Wayne Boyer <wayne.boyer at intel.com>
Commit-Queue: Wayne Boyer <wayne.boyer at intel.com>

Conflicts:
	drivers/gpu/drm/i915/intel_panel.c
---
 drivers/gpu/drm/i915/intel_panel.c |   21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 40e0cb08..b3327d0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1080,15 +1080,24 @@ static int vlv_setup_backlight(struct intel_connector *connector)
 	u32 ctl, ctl2, val;
 
 	for_each_pipe(pipe) {
-		u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe));
+		u32 duty = I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
+		u32 freq = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 
-		/* Skip if the modulation freq is already set */
-		if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK)
+		if (freq) {
+			/* Skip if the modulation freq is already set */
 			continue;
+		}
+
+		if (WARN_ON(pipe == PIPE_A)) {
+			/* Assume BLC for pipe A is the default. Therefore, A
+			 * must be non-zero. */
+			freq = (VLV_DEFAULT_BACKLIGHT_MOD_FREQ << 16);
+		} else
+			freq = I915_READ(VLV_BLC_PWM_CTL(PIPE_A)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
 
-		cur_val &= BACKLIGHT_DUTY_CYCLE_MASK;
-		I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) |
-			   cur_val);
+		if (WARN_ON(freq == 0))
+			freq = (VLV_DEFAULT_BACKLIGHT_MOD_FREQ << 16);
+		I915_WRITE(VLV_BLC_PWM_CTL(pipe), freq | duty);
 	}
 
 	ctl2 = I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
-- 
1.7.9.5