[Intel-gfx] [PATCH 22/40] drm/i915: Add chv port D TX wells

[Daniel Vetter]

On Tue, Jul 29, 2014 at 12:54:36PM +0300, Imre Deak wrote:
> On Mon, 2014-07-28 at 18:19 +0300, Ville Syrjälä wrote:
> > On Fri, Jul 25, 2014 at 04:30:29PM +0300, Imre Deak wrote:
> > > On Sat, 2014-06-28 at 02:04 +0300, ville.syrjala at linux.intel.com wrote:
> > > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > > 
> > > > Add the TX wells for port D. The Punit subsystem numbers are a total
> > > > guess at this time. Also I'm not sure these even exist. Certainly the
> > > > Punit in current hardware doesn't deal with these.
> > > > 
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
> > > >  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
> > > >  2 files changed, 27 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 3d1fef4..191df9e 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -525,6 +525,10 @@ enum punit_power_well {
> > > >  	PUNIT_POWER_WELL_DPIO_RX0		= 10,
> > > >  	PUNIT_POWER_WELL_DPIO_RX1		= 11,
> > > >  	PUNIT_POWER_WELL_DPIO_CMN_D		= 12,
> > > > +	/* FIXME: guesswork below */
> > > > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_01	= 13,
> > > > +	PUNIT_POWER_WELL_DPIO_TX_D_LANES_23	= 14,
> > > > +	PUNIT_POWER_WELL_DPIO_RX2		= 15,
> > > >  
> > > >  	PUNIT_POWER_WELL_NUM,
> > > >  };
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index cae936c..55f3e6b 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -6540,6 +6540,15 @@ EXPORT_SYMBOL_GPL(i915_release_power_well);
> > > >  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > > >  	BIT(POWER_DOMAIN_INIT))
> > > >  
> > > > +#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS (	\
> > > > +	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
> > > > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > > > +	BIT(POWER_DOMAIN_INIT))
> > > > +
> > > > +#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS (	\
> > > > +	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
> > > 
> > > Atm, for all other ports we power up all lanes regardless of the actual
> > > configuration (until the PHY side setup is proved to work fine). So for
> > > consistency I'd do the same here too. With that change:
> > 
> > We do that here too. '.domains = 01 | 23' for both tx-d wells. Or am I
> > missing something?
> 
> Ah, right I should've read a couple of lines below. So my above comment
> can be ignored and my r-b applies as-is.
> 
> > > Reviewed-by: Imre Deak <imre.deak at intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch