[Intel-gfx] [PATCH 08/40] drm/i915: Leave DPLL ref clocks on

[Jesse Barnes]

On Sat, 28 Jun 2014 02:03:59 +0300
ville.syrjala at linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> We enable the DPLL refclock already when bringing up the cmnlane power
> well, so also leave it on when otherwise disabling the DPLL.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4abf8b6f..a430699f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1709,7 +1709,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	assert_pipe_disabled(dev_priv, pipe);
>  
>  	/* Set PLL en = 0 */
> -	val = DPLL_SSC_REF_CLOCK_CHV;
> +	val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
>  	if (pipe != PIPE_A)
>  		val |= DPLL_INTEGRATED_CRI_CLK_VLV;
>  	I915_WRITE(DPLL(pipe), val);

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center