[Intel-gfx] [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV

Paulo Zanoni przanoni at gmail.com
Thu Jul 31 17:08:09 CEST 2014


2014-06-27 20:04 GMT-03:00  <ville.syrjala at linux.intel.com>:
> From: Zhenyu Wang <zhenyuw at linux.intel.com>
>

I guess this affects both VLV and CHV, but my CHV docs still contain
16/32 instead of 32/64. I didn't check any VLV docs. Any pointers, or
an explanation on the commit message?


> Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++++++---------------------
>  drivers/gpu/drm/i915/intel_pm.c | 12 +++++-----
>  2 files changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 191df9e..7ab5a03 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3909,47 +3909,47 @@ enum punit_power_well {
>
>  /* drain latency register values*/
>  #define DRAIN_LATENCY_PRECISION_32     32
> -#define DRAIN_LATENCY_PRECISION_16     16
> +#define DRAIN_LATENCY_PRECISION_64     64
>  #define VLV_DDL1                       (VLV_DISPLAY_BASE + 0x70050)
> -#define DDL_CURSORA_PRECISION_32       (1<<31)
> -#define DDL_CURSORA_PRECISION_16       (0<<31)
> +#define DDL_CURSORA_PRECISION_64       (1<<31)
> +#define DDL_CURSORA_PRECISION_32       (0<<31)
>  #define DDL_CURSORA_SHIFT              24
> -#define DDL_SPRITEB_PRECISION_32       (1<<23)
> -#define DDL_SPRITEB_PRECISION_16       (0<<23)
> +#define DDL_SPRITEB_PRECISION_64       (1<<23)
> +#define DDL_SPRITEB_PRECISION_32       (0<<23)
>  #define DDL_SPRITEB_SHIFT              16
> -#define DDL_SPRITEA_PRECISION_32       (1<<15)
> -#define DDL_SPRITEA_PRECISION_16       (0<<15)
> +#define DDL_SPRITEA_PRECISION_64       (1<<15)
> +#define DDL_SPRITEA_PRECISION_32       (0<<15)
>  #define DDL_SPRITEA_SHIFT              8
> -#define DDL_PLANEA_PRECISION_32                (1<<7)
> -#define DDL_PLANEA_PRECISION_16                (0<<7)
> +#define DDL_PLANEA_PRECISION_64                (1<<7)
> +#define DDL_PLANEA_PRECISION_32                (0<<7)
>  #define DDL_PLANEA_SHIFT               0
>
>  #define VLV_DDL2                       (VLV_DISPLAY_BASE + 0x70054)
> -#define DDL_CURSORB_PRECISION_32       (1<<31)
> -#define DDL_CURSORB_PRECISION_16       (0<<31)
> +#define DDL_CURSORB_PRECISION_64       (1<<31)
> +#define DDL_CURSORB_PRECISION_32       (0<<31)
>  #define DDL_CURSORB_SHIFT              24
> -#define DDL_SPRITED_PRECISION_32       (1<<23)
> -#define DDL_SPRITED_PRECISION_16       (0<<23)
> +#define DDL_SPRITED_PRECISION_64       (1<<23)
> +#define DDL_SPRITED_PRECISION_32       (0<<23)
>  #define DDL_SPRITED_SHIFT              16
> -#define DDL_SPRITEC_PRECISION_32       (1<<15)
> -#define DDL_SPRITEC_PRECISION_16       (0<<15)
> +#define DDL_SPRITEC_PRECISION_64       (1<<15)
> +#define DDL_SPRITEC_PRECISION_32       (0<<15)
>  #define DDL_SPRITEC_SHIFT              8
> -#define DDL_PLANEB_PRECISION_32                (1<<7)
> -#define DDL_PLANEB_PRECISION_16                (0<<7)
> +#define DDL_PLANEB_PRECISION_64                (1<<7)
> +#define DDL_PLANEB_PRECISION_32                (0<<7)
>  #define DDL_PLANEB_SHIFT               0
>
>  #define VLV_DDL3                       (VLV_DISPLAY_BASE + 0x70058)
> -#define DDL_CURSORC_PRECISION_32       (1<<31)
> -#define DDL_CURSORC_PRECISION_16       (0<<31)
> +#define DDL_CURSORC_PRECISION_64       (1<<31)
> +#define DDL_CURSORC_PRECISION_32       (0<<31)
>  #define DDL_CURSORC_SHIFT              24
> -#define DDL_SPRITEF_PRECISION_32       (1<<23)
> -#define DDL_SPRITEF_PRECISION_16       (0<<23)
> +#define DDL_SPRITEF_PRECISION_64       (1<<23)
> +#define DDL_SPRITEF_PRECISION_32       (0<<23)
>  #define DDL_SPRITEF_SHIFT              16
> -#define DDL_SPRITEE_PRECISION_32       (1<<15)
> -#define DDL_SPRITEE_PRECISION_16       (0<<15)
> +#define DDL_SPRITEE_PRECISION_64       (1<<15)
> +#define DDL_SPRITEE_PRECISION_32       (0<<15)
>  #define DDL_SPRITEE_SHIFT              8
> -#define DDL_PLANEC_PRECISION_32                (1<<7)
> -#define DDL_PLANEC_PRECISION_16                (0<<7)
> +#define DDL_PLANEC_PRECISION_64                (1<<7)
> +#define DDL_PLANEC_PRECISION_32                (0<<7)
>  #define DDL_PLANEC_SHIFT               0
>
>  /* FIFO watermark sizes etc */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 55f3e6b..9413184 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1253,13 +1253,13 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
>
>         entries = (clock / 1000) * pixel_size;
>         *plane_prec_mult = (entries > 256) ?
> -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
>                                                      pixel_size);
>
>         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
>         *cursor_prec_mult = (entries > 256) ?
> -               DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +               DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;
>         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
>
>         return true;
> @@ -1285,9 +1285,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
>                                       &cursor_prec_mult, &cursora_dl)) {
>                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
> +                       DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_64;
>                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
> +                       DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_64;
>
>                 I915_WRITE(VLV_DDL1, cursora_prec |
>                                 (cursora_dl << DDL_CURSORA_SHIFT) |
> @@ -1298,9 +1298,9 @@ static void vlv_update_drain_latency(struct drm_device *dev)
>         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
>                                       &cursor_prec_mult, &cursorb_dl)) {
>                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
> +                       DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_64;
>                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> -                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
> +                       DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_64;
>
>                 I915_WRITE(VLV_DDL2, cursorb_prec |
>                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
> --
> 1.8.5.5
>
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-- 
Paulo Zanoni



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