[Intel-gfx] [PATCH v10] drm/i915: Replaced Blitter ring based flips with MMIO flips

[Chris Wilson]

On Sun, Jun 01, 2014 at 04:43:13PM +0530, sourab.gupta at intel.com wrote:
> From: Sourab Gupta <sourab.gupta at intel.com>
> 
> This patch enables the framework for using MMIO based flip calls,
> in contrast with the CS based flip calls which are being used currently.
> 
> MMIO based flip calls can be enabled on architectures where
> Render and Blitter engines reside in different power wells. The
> decision to use MMIO flips can be made based on workloads to give
> 100% residency for Media power well.
> 
> v2: The MMIO flips now use the interrupt driven mechanism for issuing the
> flips when target seqno is reached. (Incorporating Ville's idea)
> 
> v3: Rebasing on latest code. Code restructuring after incorporating
> Damien's comments
> 
> v4: Addressing Ville's review comments
>     -general cleanup
>     -updating only base addr instead of calling update_primary_plane
>     -extending patch for gen5+ platforms
> 
> v5: Addressed Ville's review comments
>     -Making mmio flip vs cs flip selection based on module parameter
>     -Adding check for DRIVER_MODESET feature in notify_ring before calling
>      notify mmio flip.
>     -Other changes mostly in function arguments
> 
> v6: -Having a seperate function to check condition for using mmio flips (Ville)
>     -propogating error code from i915_gem_check_olr (Ville)
> 
> v7: -Adding __must_check with i915_gem_check_olr (Chris)
>     -Renaming mmio_flip_data to mmio_flip (Chris)
>     -Rebasing on latest nightly
> 
> v8: -Rebasing on latest code
>     -squash 3rd patch in series(mmio setbase vs page flip race) with this patch
>     -Added new tiling mode update in intel_do_mmio_flip (Chris)
> 
> v9: -check for obj->last_write_seqno being 0 instead of obj->ring being NULL in
> intel_postpone_flip, as this is a more restrictive condition (Chris)
> 
> v10: -Applied Chris's suggestions for squashing patches 2,3 into this patch.
> These patches make the selection of CS vs MMIO flip at the page flip time, and
> make the module parameter for using mmio flips as tristate, the states being
> 'force CS flips', 'force mmio flips', 'driver discretion'.
> Changed the logic for driver discretion (Chris)
> 
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Sourab Gupta <sourab.gupta at intel.com>
> Signed-off-by: Akash Goel <akash.goel at intel.com>
Tested-by: Chris Wilson <chris at chris-wilson.co.uk> # snb, ivb

Really happy with this now, just a few irrelevant bikesheds.

> -static int
> +__must_check int
>  i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
>  {

Only the declaration requires the __must_check attribute, we don't need
it here as well.

>  	int ret;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4ef6423..e0edb1f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1218,6 +1218,9 @@ static void notify_ring(struct drm_device *dev,
>  
>  	trace_i915_gem_request_complete(ring);
>  
> +	if (drm_core_check_feature(dev, DRIVER_MODESET))
> +		intel_notify_mmio_flip(ring);
> +

I wish Ville had suggested making UMS do the extra work of setting up
the spinlock instead.

> +static bool use_mmio_flip(struct intel_engine_cs *ring,
> +			  struct drm_i915_gem_object *obj)
> +{
> +	 /* This is not being used for older platforms, because
> +	 * non-availability of flip done interrupt forces us to use
> +	 * CS flips. Older platforms derive flip done using some clever
> +	 * tricks involving the flip_pending status bits and vblank irqs.
> +	 * So using MMIO flips there would disrupt this mechanism.
> +	 */
> +
> +	if (INTEL_INFO(ring->dev)->gen < 5)
> +		return false;
> +
> +	if (i915.use_mmio_flip < 0)
> +		return false;
> +	else if (i915.use_mmio_flip > 0)
> +		return true;
> +	else
> +		return ring != obj->ring;
> +}

Check whitespace.

> +
> +static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
> +{
> +	struct drm_device *dev = intel_crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_framebuffer *intel_fb =
> +		to_intel_framebuffer(intel_crtc->base.primary->fb);
> +	struct drm_i915_gem_object *obj = intel_fb->obj;
> +	u32 dspcntr;
> +	u32 reg;
> +
> +	intel_mark_page_flip_active(intel_crtc);
> +
> +	reg = DSPCNTR(intel_crtc->plane);
> +	dspcntr = I915_READ(reg);
> +
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		if (obj->tiling_mode != I915_TILING_NONE)
> +			dspcntr |= DISPPLANE_TILED;
> +		else
> +			dspcntr &= ~DISPPLANE_TILED;
> +	}
> +	I915_WRITE(reg, dspcntr);
> +
> +	I915_WRITE(DSPSURF(intel_crtc->plane),
> +			intel_crtc->unpin_work->gtt_offset);
> +	POSTING_READ(DSPSURF(intel_crtc->plane));
> +}
> +
> +static int intel_postpone_flip(struct drm_i915_gem_object *obj)
> +{
        struct intel_engine_cs *ring = obj->ring; // will save our eyes
> +	int ret;
> +

        // I had to go back and check the locking, so save the
	// next person the same task.
        lockdep_assert_held(&obj->base.dev->struct_mutex);

> +	if (!obj->last_write_seqno)
> +		return 0;
> +
> +	if (i915_seqno_passed(obj->ring->get_seqno(obj->ring, true),
> +				obj->last_write_seqno))
> +		return 0;
> +
> +	ret = i915_gem_check_olr(obj->ring, obj->last_write_seqno);
> +	if (ret)
> +		return ret;
> +
> +	if (WARN_ON(!obj->ring->irq_get(obj->ring)))
> +		return 0;
> +
> +	return 1;
> +}
> +
> +void intel_notify_mmio_flip(struct intel_engine_cs *ring)
> +{
> +	struct drm_i915_private *dev_priv = ring->dev->dev_private;

	struct drm_i915_private *dev_priv = to_i915(ring->dev);

> +	struct intel_crtc *intel_crtc;
> +	unsigned long irq_flags;
> +	u32 seqno;
> +
> +	seqno = ring->get_seqno(ring, false);
> +
> +	spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
> +	for_each_intel_crtc(ring->dev, intel_crtc) {
> +		struct intel_mmio_flip *mmio_flip;
> +
> +		mmio_flip = &intel_crtc->mmio_flip;
> +		if (mmio_flip->seqno == 0)
> +			continue;
> +
> +		if (ring->id != mmio_flip->ring_id)
> +			continue;
> +
> +		if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
> +			intel_do_mmio_flip(intel_crtc);
> +			mmio_flip->seqno = 0;
> +			ring->irq_put(ring);
> +		}
> +	}
> +	spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
> +}
> +
> +static int intel_queue_mmio_flip(struct drm_device *dev,
> +		struct drm_crtc *crtc,
> +		struct drm_framebuffer *fb,
> +		struct drm_i915_gem_object *obj,
> +		struct intel_engine_cs *ring,
> +		uint32_t flags)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	unsigned long irq_flags;
> +	int ret;
> +
> +	if (WARN_ON(intel_crtc->mmio_flip.seqno))
> +		return -EBUSY;
> +
> +	ret = intel_postpone_flip(obj);
> +	if (ret < 0)
> +		return ret;
> +	 if (ret == 0) {
> +		intel_do_mmio_flip(intel_crtc);
> +		return 0;
> +	}
> +
> +	spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
> +	intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
> +	intel_crtc->mmio_flip.ring_id = obj->ring->id;
> +	spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
> +
> +	/* Double check to catch cases where irq fired before
> +	 * mmio flip data was ready
> +	 */
> +	intel_notify_mmio_flip(obj->ring);
> +	return 0;
> +}

Check whitespace.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre