[Intel-gfx] Breaking suspend/resume by the Pipe A quirk

Daniel Vetter daniel at ffwll.ch
Tue Jun 3 16:45:09 CEST 2014


On Tue, Jun 03, 2014 at 04:38:40PM +0200, Thomas Richter wrote:
> Hi Daniel, dear intel experts,
> 
> >We've put a crtc restriction on VGA (it needs to be crtc 0) to work around
> >some issues. DVI/LVDS should work on crtc 1. You can set this with the
> >--crtc knob for xrandr.
> >
> Unfortunately, I cannot. Whenever I put DVI1 (which is connected to the
> internal screen) on crt1,
> the internal screen stays blank. Where would I need to modify the sources to
> test whether I could try
> the reverse, i.e. drive VGA with crt1? (That's not possibly, as you say).


diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 22d8347f7838..80e3f1fc1ad6 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -833,10 +833,7 @@ void intel_crt_init(struct drm_device *dev)
 
 	crt->base.type = INTEL_OUTPUT_ANALOG;
 	crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
-	if (IS_I830(dev))
-		crt->base.crtc_mask = (1 << 0);
-	else
-		crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+	crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 
 	if (IS_GEN2(dev))
 		connector->interlace_allowed = 0;

> I neither found a way to un-clone the screens, i.e. you can say that xrandr
> should place VGA1 to the left
> of DVI1, but xrandr --verbose still claims that VGA1 and DVI1 are clones of
> each other. The best you get is
> a blank screen on DVI1, and a high-resolution display on VGA1, but not two
> independent monitors with
> differing resolutions.

Yeah, if you can't move the panel to the crtc 1 only cloning will be
possible.

> Here is the configuration when booting. It clones the monitors, even though
> the bios says "internal only". Never mind,
> this works:

Yeah, both connectors use CRTC 0. Have you tried what happens if you:
- disable DVI1 first (--off)
- then enable it on crtc 1?

Cheers, Daniel

> 
> (p.s. any news from the watermark-alignment patch? Is this acceptable?)
> 
> Screen 0: minimum 320 x 200, current 2048 x 1536, maximum 2048 x 2048
> VGA1 disconnected 2048x1536+0+0 (0x48) normal (normal left inverted right x
> axis y axis) 0mm x 0mm panning 2048x1536+0+0
>     Identifier: 0x41
>     Timestamp:  463642
>     Subpixel:   unknown
>     Gamma:      1.0:1.0:1.0
>     Brightness: 1.0
>     Clones:     DVI1
>     CRTC:       0
>     CRTCs:      0
>     Panning:    2048x1536+0+0
>     Tracking:   0x0+0+0
>     Border:     0/0/0/0
>     Transform:  1.000000 0.000000 0.000000
>                 0.000000 1.000000 0.000000
>                 0.000000 0.000000 1.000000
>                filter:
> DVI1 connected 2048x1536+0+0 (0x48) normal (normal left inverted right x
> axis y axis) 0mm x 0mm panning 2048x1536+0+0
>     Identifier: 0x42
>     Timestamp:  463642
>     Subpixel:   horizontal rgb
>     Gamma:      1.0:1.0:1.0
>     Brightness: 1.0
>     Clones:     VGA1
>     CRTC:       0
>     CRTCs:      0 1
>     Panning:    2048x1536+0+0
>     Tracking:   0x0+0+0
>     Border:     0/0/0/0
>     Transform:  1.000000 0.000000 0.000000
>                 0.000000 1.000000 0.000000
>                 0.000000 0.000000 1.000000
>                filter:
>   1024x768 (0x48)   65.0MHz -HSync -VSync *current
>         h: width  1024 start 1048 end 1184 total 1344 skew    0 clock
> 48.4KHz
>         v: height  768 start  771 end  777 total  806           clock
> 60.0Hz
>   800x600 (0x4c)   40.0MHz +HSync +VSync
>         h: width   800 start  840 end  968 total 1056 skew    0 clock
> 37.9KHz
>         v: height  600 start  601 end  605 total  628           clock
> 60.3Hz
>   800x600 (0x4d)   36.0MHz +HSync +VSync
>         h: width   800 start  824 end  896 total 1024 skew    0 clock
> 35.2KHz
>         v: height  600 start  601 end  603 total  625           clock
> 56.2Hz
>   640x480 (0x52)   25.2MHz -HSync -VSync
>         h: width   640 start  656 end  752 total  800 skew    0 clock
> 31.5KHz
>         v: height  480 start  489 end  492 total  525           clock
> 59.9Hz
> 
> --
> 
> And this is the register dump:
> 
>                  DCC: 0x00000000 (`7rbFtndu)
>            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled,
> ch0 enh disabled, flex disabled, ep not present)
>               C0DRB0: 0x00000000 (0x0000)
>               C0DRB1: 0x00000000 (0x0000)
>               C0DRB2: 0x00000000 (0x0000)
>               C0DRB3: 0x00000000 (0x0000)
>               C1DRB0: 0x00000000 (0x0000)
>               C1DRB1: 0x00000000 (0x0000)
>               C1DRB2: 0x00000000 (0x0000)
>               C1DRB3: 0x00000000 (0x0000)
>              C0DRA01: 0x00000000 (0x0000)
>              C0DRA23: 0x00000000 (0x0000)
>              C1DRA01: 0x00000000 (0x0000)
>              C1DRA23: 0x00000000 (0x0000)
>           PGETBL_CTL: 0x3ff60001
>    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 =
> 4)
>            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input
> buffer disabled)
>         CACHE_MODE_0: 0x00000000
>              D_STATE: 0x00000000
>        DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT)
>       RENCLK_GATE_D1: 0x00000000
>       RENCLK_GATE_D2: 0x00000000
>                SDVOB: 0x80004084 (enabled, pipe A, stall disabled, detected)
>                SDVOC: 0x90004084 (enabled, pipe A, stall disabled, detected)
>              SDVOUDI: 0x00000000
>               DSPARB: 0x00017e5f
>               DSPFW1: 0x00000000
>               DSPFW2: 0x00000000
>               DSPFW3: 0x00000000
>                 ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
>                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync,
> -vsync)
>                 DVOB: 0x80004084 (enabled, pipe A, no stall, -hsync, -vsync)
>                 DVOC: 0x90004084 (enabled, pipe A, stall, -hsync, -vsync)
>          DVOA_SRCDIM: 0x00000000
>          DVOB_SRCDIM: 0x00000000
>          DVOC_SRCDIM: 0x00000000
>           PP_CONTROL: 0x00000000 (power target: off)
>            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>         PP_ON_DELAYS: 0x00000000
>        PP_OFF_DELAYS: 0x00000000
>           PP_DIVISOR: 0x00000000
>         PFIT_CONTROL: 0x00000000
>      PFIT_PGM_RATIOS: 0x00000000
>      PORT_HOTPLUG_EN: 0x00000000
>    PORT_HOTPLUG_STAT: 0x00000000
>             DSPACNTR: 0x98000000 (enabled, pipe A)
>           DSPASTRIDE: 0x00002000 (8192 bytes)
>              DSPAPOS: 0x00000000 (0, 0)
>             DSPASIZE: 0x02ff03ff (1024, 768)
>             DSPABASE: 0x03000000
>             DSPASURF: 0x00000000
>          DSPATILEOFF: 0x00000000
>            PIPEACONF: 0x80000000 (enabled, single-wide)
>             PIPEASRC: 0x03ff02ff (1024, 768)
>            PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS
> SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>    PIPEA_GMCH_DATA_M: 0x00000000
>    PIPEA_GMCH_DATA_N: 0x00000000
>      PIPEA_DP_LINK_M: 0x00000000
>      PIPEA_DP_LINK_N: 0x00000000
>        CURSOR_A_BASE: 0x35a28000
>     CURSOR_A_CONTROL: 0x04000027
>    CURSOR_A_POSITION: 0x000a0271
>                 FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>                 FPA1: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>               DPLL_A: 0xd0820000 (enabled, dvo, default clock, DAC/serial
> mode, p1 = 4, p2 = 4)
>            DPLL_A_MD: 0x00000000
>             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>             VTOTAL_A: 0x032502ff (768 active, 806 total)
>             VBLANK_A: 0x032502ff (768 start, 806 end)
>              VSYNC_A: 0x03080302 (771 start, 777 end)
>            BCLRPAT_A: 0x00000000
>         VSYNCSHIFT_A: 0x00000000
>             DSPBCNTR: 0x19000000 (disabled, pipe B)
>           DSPBSTRIDE: 0x00001400 (5120 bytes)
>              DSPBPOS: 0x00000000 (0, 0)
>             DSPBSIZE: 0x02ff03ff (1024, 768)
>             DSPBBASE: 0x00060000
>             DSPBSURF: 0x00000000
>          DSPBTILEOFF: 0x00000000
>            PIPEBCONF: 0x00000000 (disabled, single-wide)
>             PIPEBSRC: 0x03ff02ff (1024, 768)
>            PIPEBSTAT: 0x10000000 (status: CRC_DONE_ENABLE)
>    PIPEB_GMCH_DATA_M: 0x00000000
>    PIPEB_GMCH_DATA_N: 0x00000000
>      PIPEB_DP_LINK_M: 0x00000000
>      PIPEB_DP_LINK_N: 0x00000000
>        CURSOR_B_BASE: 0x00000000
>     CURSOR_B_CONTROL: 0x10000000
>    CURSOR_B_POSITION: 0x009f801d
>                 FPB0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>                 FPB1: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>               DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock,
> DAC/serial mode, p1 = 2, p2 = 2)
>            DPLL_B_MD: 0x00000000
>             HTOTAL_B: 0x053f03ff (1024 active, 1344 total)
>             HBLANK_B: 0x053f03ff (1024 start, 1344 end)
>              HSYNC_B: 0x049f0417 (1048 start, 1184 end)
>             VTOTAL_B: 0x032502ff (768 active, 806 total)
>             VBLANK_B: 0x032502ff (768 start, 806 end)
>              VSYNC_B: 0x03080302 (771 start, 777 end)
>            BCLRPAT_B: 0x00000000
>         VSYNCSHIFT_B: 0x00000000
>    VCLK_DIVISOR_VGA0: 0x00021207
>    VCLK_DIVISOR_VGA1: 0x00031406
>        VCLK_POST_DIV: 0x0000888b
>             VGACNTRL: 0x80000000 (disabled)
>               TV_CTL: 0x00000000
>               TV_DAC: 0x00000000
>             TV_CSC_Y: 0x00000000
>            TV_CSC_Y2: 0x00000000
>             TV_CSC_U: 0x00000000
>            TV_CSC_U2: 0x00000000
>             TV_CSC_V: 0x00000000
>            TV_CSC_V2: 0x00000000
>         TV_CLR_KNOBS: 0x00000000
>         TV_CLR_LEVEL: 0x00000000
>           TV_H_CTL_1: 0x00000000
>           TV_H_CTL_2: 0x00000000
>           TV_H_CTL_3: 0x00000000
>           TV_V_CTL_1: 0x00000000
>           TV_V_CTL_2: 0x00000000
>           TV_V_CTL_3: 0x00000000
>           TV_V_CTL_4: 0x00000000
>           TV_V_CTL_5: 0x00000000
>           TV_V_CTL_6: 0x00000000
>           TV_V_CTL_7: 0x00000000
>          TV_SC_CTL_1: 0x00000000
>          TV_SC_CTL_2: 0x00000000
>          TV_SC_CTL_3: 0x00000000
>           TV_WIN_POS: 0x00000000
>          TV_WIN_SIZE: 0x00000000
>      TV_FILTER_CTL_1: 0x00000000
>      TV_FILTER_CTL_2: 0x00000000
>      TV_FILTER_CTL_3: 0x00000000
>        TV_CC_CONTROL: 0x00000000
>           TV_CC_DATA: 0x00000000
>          TV_H_LUMA_0: 0x00000000
>         TV_H_LUMA_59: 0x00000000
>        TV_H_CHROMA_0: 0x00000000
>       TV_H_CHROMA_59: 0x00000000
>         FBC_CFB_BASE: 0x00000000
>          FBC_LL_BASE: 0x00000000
>          FBC_CONTROL: 0x00000000
>          FBC_COMMAND: 0x00000000
>           FBC_STATUS: 0x00000000
>         FBC_CONTROL2: 0x00000000
>        FBC_FENCE_OFF: 0x00000000
>          FBC_MOD_NUM: 0x00000000
>              MI_MODE: 0x00000000
>         MI_ARB_STATE: 0x00000000
>       MI_RDRET_STATE: 0x00000000
>              ECOSKPD: 0x00000307
>                 DP_B: 0x00000000
>       DPB_AUX_CH_CTL: 0x00000000
>     DPB_AUX_CH_DATA1: 0x00000000
>     DPB_AUX_CH_DATA2: 0x00000000
>     DPB_AUX_CH_DATA3: 0x00000000
>     DPB_AUX_CH_DATA4: 0x00000000
>     DPB_AUX_CH_DATA5: 0x00000000
>                 DP_C: 0x00000000
>       DPC_AUX_CH_CTL: 0x00000000
>     DPC_AUX_CH_DATA1: 0x00000000
>     DPC_AUX_CH_DATA2: 0x00000000
>     DPC_AUX_CH_DATA3: 0x00000000
>     DPC_AUX_CH_DATA4: 0x00000000
>     DPC_AUX_CH_DATA5: 0x00000000
>                 DP_D: 0x00000000
>       DPD_AUX_CH_CTL: 0x00000000
>     DPD_AUX_CH_DATA1: 0x00000000
>     DPD_AUX_CH_DATA2: 0x00000000
>     DPD_AUX_CH_DATA3: 0x00000000
>     DPD_AUX_CH_DATA4: 0x00000000
>     DPD_AUX_CH_DATA5: 0x00000000
>           AUD_CONFIG: 0x00000000
>     AUD_HDMIW_STATUS: 0x00000000
>       AUD_CONV_CHCNT: 0x00000000
>        VIDEO_DIP_CTL: 0x00000000
>        AUD_PINW_CNTR: 0x00000000
>          AUD_CNTL_ST: 0x00000000
>          AUD_PIN_CAP: 0x00000000
>         AUD_PINW_CAP: 0x00000000
>   AUD_PINW_UNSOLRESP: 0x00000000
>     AUD_OUT_DIG_CNVT: 0x00000000
>        AUD_OUT_CWCAP: 0x00000000
>          AUD_GRP_CAP: 0x00000000
>             FENCE  0: 0x01000351 (enabled, X tiled, 16384 pitch, 0x01000000
> - 0x01800000 (8192kb))
>             FENCE  1: 0x05000561 (enabled, X tiled, 32768 pitch, 0x05000000
> - 0x07000000 (32768kb))
>             FENCE  2: 0x01600131 (enabled, X tiled, 4096 pitch, 0x01600000 -
> 0x01800000 (2048kb))
>             FENCE  3: 0x00000000 (disabled)
>             FENCE  4: 0x00000000 (disabled)
>             FENCE  5: 0x03000561 (enabled, X tiled, 32768 pitch, 0x03000000
> - 0x05000000 (32768kb))
>             FENCE  6: 0x00000000 (disabled)
>             FENCE  7: 0x00000000 (disabled)
>             FENCE  8: 0x00000000 (disabled)
>             FENCE  9: 0x00000000 (disabled)
>            FENCE  10: 0x00000000 (disabled)
>            FENCE  11: 0x00000000 (disabled)
>            FENCE  12: 0x00000048 (disabled)
>            FENCE  13: 0x00000002 (disabled)
>            FENCE  14: 0x00000000 (disabled)
>            FENCE  15: 0x00000000 (disabled)
>        FENCE START 0: 0x00000000 (disabled)
>          FENCE END 0: 0x00000000 (disabled)
>        FENCE START 1: 0x00000000 (disabled)
>          FENCE END 1: 0x00000000 (disabled)
>        FENCE START 2: 0x00000048 (disabled)
>          FENCE END 2: 0x00000002 (disabled)
>        FENCE START 3: 0x00000000 (disabled)
>          FENCE END 3: 0x00000000 (disabled)
>        FENCE START 4: 0x00000000 (disabled)
>          FENCE END 4: 0x00000000 (disabled)
>        FENCE START 5: 0x00000000 (disabled)
>          FENCE END 5: 0x00000000 (disabled)
>        FENCE START 6: 0x00000000 (disabled)
>          FENCE END 6: 0x00000000 (disabled)
>        FENCE START 7: 0x00000000 (disabled)
>          FENCE END 7: 0x00000000 (disabled)
>        FENCE START 8: 0x00000000 (disabled)
>          FENCE END 8: 0x00000000 (disabled)
>        FENCE START 9: 0x00000000 (disabled)
>          FENCE END 9: 0x00000000 (disabled)
>       FENCE START 10: 0x00000000 (disabled)
>         FENCE END 10: 0x00000000 (disabled)
>       FENCE START 11: 0x00000000 (disabled)
>         FENCE END 11: 0x00000000 (disabled)
>       FENCE START 12: 0x00000000 (disabled)
>         FENCE END 12: 0x00000000 (disabled)
>       FENCE START 13: 0x00000000 (disabled)
>         FENCE END 13: 0x00000000 (disabled)
>       FENCE START 14: 0x00000000 (disabled)
>         FENCE END 14: 0x00000000 (disabled)
>       FENCE START 15: 0x00000000 (disabled)
>         FENCE END 15: 0x00000000 (disabled)
>              INST_PM: 0x00000000
> pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4
> pipe B dot 260000 n 4 m1 21 m2 13 p1 2 p2 2
> 
> ---
> 
> If I try to move DVI1 to crtc 1, the internal screen stays blank. Then, I
> can change the resolution of the external screen, but without any
> picture on DVI1. This is what I get:
> 
> Screen 0: minimum 320 x 200, current 2048 x 1536, maximum 2048 x 2048
> VGA1 connected 2048x1536+0+0 (0x46) normal (normal left inverted right x
> axis y axis) 338mm x 270mm panning 2048x1536+0+0
>     Identifier: 0x41
>     Timestamp:  258836
>     Subpixel:   unknown
>     Gamma:      1.0:1.0:1.0
>     Brightness: 1.0
>     Clones:     DVI1
>     CRTC:       0
>     CRTCs:      0
>     Panning:    2048x1536+0+0
>     Tracking:   0x0+0+0
>     Border:     0/0/0/0
>     Transform:  1.000000 0.000000 0.000000
>                 0.000000 1.000000 0.000000
>                 0.000000 0.000000 1.000000
>                filter:
>     EDID:
>         00ffffffffffff004c2d1d0037314847
>         1a0c01030f221b8cea6f8ba25a4d9424
>         1a5156bfef8081806140454031400101
>         010101010101302a009851002a403070
>         1300520e1100001e000000fd0038551e
>         510e000a202020202020000000fc0053
>         796e634d61737465720a2020000000ff
>         0048344c543630343930380a20200054
>   1280x1024 (0x43)  108.0MHz +HSync +VSync +preferred
>         h: width  1280 start 1328 end 1440 total 1688 skew    0 clock
> 64.0KHz
>         v: height 1024 start 1025 end 1028 total 1066           clock
> 60.0Hz
>   1280x1024 (0x44)  135.0MHz +HSync +VSync
>         h: width  1280 start 1296 end 1440 total 1688 skew    0 clock
> 80.0KHz
>         v: height 1024 start 1025 end 1028 total 1066           clock
> 75.0Hz
>   1152x864 (0x45)  108.0MHz +HSync +VSync
>         h: width  1152 start 1216 end 1344 total 1600 skew    0 clock
> 67.5KHz
>         v: height  864 start  865 end  868 total  900           clock
> 75.0Hz
>   1024x768 (0x46)   78.8MHz +HSync +VSync *current
>         h: width  1024 start 1040 end 1136 total 1312 skew    0 clock
> 60.1KHz
>         v: height  768 start  769 end  772 total  800           clock
> 75.1Hz
>   1024x768 (0x47)   75.0MHz -HSync -VSync
>         h: width  1024 start 1048 end 1184 total 1328 skew    0 clock
> 56.5KHz
>         v: height  768 start  771 end  777 total  806           clock
> 70.1Hz
>   1024x768 (0x48)   65.0MHz -HSync -VSync
>         h: width  1024 start 1048 end 1184 total 1344 skew    0 clock
> 48.4KHz
>         v: height  768 start  771 end  777 total  806           clock
> 60.0Hz
>   832x624 (0x49)   57.3MHz -HSync -VSync
>         h: width   832 start  864 end  928 total 1152 skew    0 clock
> 49.7KHz
>         v: height  624 start  625 end  628 total  667           clock
> 74.6Hz
>   800x600 (0x4a)   50.0MHz +HSync +VSync
>         h: width   800 start  856 end  976 total 1040 skew    0 clock
> 48.1KHz
>         v: height  600 start  637 end  643 total  666           clock
> 72.2Hz
>   800x600 (0x4b)   49.5MHz +HSync +VSync
>         h: width   800 start  816 end  896 total 1056 skew    0 clock
> 46.9KHz
>         v: height  600 start  601 end  604 total  625           clock
> 75.0Hz
>   800x600 (0x4c)   40.0MHz +HSync +VSync
>         h: width   800 start  840 end  968 total 1056 skew    0 clock
> 37.9KHz
>         v: height  600 start  601 end  605 total  628           clock
> 60.3Hz
>   800x600 (0x4d)   36.0MHz +HSync +VSync
>         h: width   800 start  824 end  896 total 1024 skew    0 clock
> 35.2KHz
>         v: height  600 start  601 end  603 total  625           clock
> 56.2Hz
>   640x480 (0x4e)   31.5MHz -HSync -VSync
>         h: width   640 start  656 end  720 total  840 skew    0 clock
> 37.5KHz
>         v: height  480 start  481 end  484 total  500           clock
> 75.0Hz
>   640x480 (0x4f)   31.5MHz -HSync -VSync
>         h: width   640 start  664 end  704 total  832 skew    0 clock
> 37.9KHz
>         v: height  480 start  489 end  491 total  520           clock
> 72.8Hz
>   640x480 (0x50)   30.2MHz -HSync -VSync
>         h: width   640 start  704 end  768 total  864 skew    0 clock
> 35.0KHz
>         v: height  480 start  483 end  486 total  525           clock
> 66.7Hz
>   640x480 (0x51)   25.2MHz -HSync -VSync
>         h: width   640 start  656 end  752 total  800 skew    0 clock
> 31.5KHz
>         v: height  480 start  490 end  492 total  525           clock
> 60.0Hz
>   640x480 (0x52)   25.2MHz -HSync -VSync
>         h: width   640 start  656 end  752 total  800 skew    0 clock
> 31.5KHz
>         v: height  480 start  489 end  492 total  525           clock
> 59.9Hz
>   720x400 (0x53)   28.3MHz -HSync +VSync
>         h: width   720 start  738 end  846 total  900 skew    0 clock
> 31.5KHz
>         v: height  400 start  412 end  414 total  449           clock
> 70.1Hz
> DVI1 connected 800x600+1024+0 (0x4c) normal (normal left inverted right x
> axis y axis) 0mm x 0mm
>     Identifier: 0x42
>     Timestamp:  258836
>     Subpixel:   horizontal rgb
>     Gamma:      1.0:1.0:1.0
>     Brightness: 1.0
>     Clones:     VGA1
>     CRTC:       1
>     CRTCs:      0 1
>     Transform:  1.000000 0.000000 0.000000
>                 0.000000 1.000000 0.000000
>                 0.000000 0.000000 1.000000
>                filter:
>   1024x768 (0x48)   65.0MHz -HSync -VSync
>         h: width  1024 start 1048 end 1184 total 1344 skew    0 clock
> 48.4KHz
>         v: height  768 start  771 end  777 total  806           clock
> 60.0Hz
>   800x600 (0x4c)   40.0MHz +HSync +VSync *current
>         h: width   800 start  840 end  968 total 1056 skew    0 clock
> 37.9KHz
>         v: height  600 start  601 end  605 total  628           clock
> 60.3Hz
>   800x600 (0x4d)   36.0MHz +HSync +VSync
>         h: width   800 start  824 end  896 total 1024 skew    0 clock
> 35.2KHz
>         v: height  600 start  601 end  603 total  625           clock
> 56.2Hz
>   640x480 (0x52)   25.2MHz -HSync -VSync
>         h: width   640 start  656 end  752 total  800 skew    0 clock
> 31.5KHz
>         v: height  480 start  489 end  492 total  525           clock
> 59.9Hz
> 
> Note that DVI1 still claims being a clone of VGA1, but the screen remains
> dark. The resolution is now a different one, but black in 800x600 is still
> black. (-: This is the register configuration:
> 
>                  DCC: 0x00000000 (`tbvqxd
> x)
>            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled,
> ch0 enh disabled, flex disabled, ep not present)
>               C0DRB0: 0x00000000 (0x0000)
>               C0DRB1: 0x00000000 (0x0000)
>               C0DRB2: 0x00000000 (0x0000)
>               C0DRB3: 0x00000000 (0x0000)
>               C1DRB0: 0x00000000 (0x0000)
>               C1DRB1: 0x00000000 (0x0000)
>               C1DRB2: 0x00000000 (0x0000)
>               C1DRB3: 0x00000000 (0x0000)
>              C0DRA01: 0x00000000 (0x0000)
>              C0DRA23: 0x00000000 (0x0000)
>              C1DRA01: 0x00000000 (0x0000)
>              C1DRA23: 0x00000000 (0x0000)
>           PGETBL_CTL: 0x3ff60001
>    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 =
> 4)
>            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input
> buffer disabled)
>         CACHE_MODE_0: 0x00000000
>              D_STATE: 0x00000000
>        DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT)
>       RENCLK_GATE_D1: 0x00000000
>       RENCLK_GATE_D2: 0x00000000
>                SDVOB: 0x80004084 (enabled, pipe A, stall disabled, detected)
>                SDVOC: 0xd000409c (enabled, pipe B, stall disabled, detected)
>              SDVOUDI: 0x00000000
>               DSPARB: 0x00017e5f
>               DSPFW1: 0x00000000
>               DSPFW2: 0x00000000
>               DSPFW3: 0x00000000
>                 ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
>                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync,
> -vsync)
>                 DVOB: 0x80004084 (enabled, pipe A, no stall, -hsync, -vsync)
>                 DVOC: 0xd000409c (enabled, pipe B, stall, +hsync, +vsync)
>          DVOA_SRCDIM: 0x00000000
>          DVOB_SRCDIM: 0x00000000
>          DVOC_SRCDIM: 0x00000000
>           PP_CONTROL: 0x00000000 (power target: off)
>            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>         PP_ON_DELAYS: 0x00000000
>        PP_OFF_DELAYS: 0x00000000
>           PP_DIVISOR: 0x00000000
>         PFIT_CONTROL: 0x00000000
>      PFIT_PGM_RATIOS: 0x00000000
>      PORT_HOTPLUG_EN: 0x00000000
>    PORT_HOTPLUG_STAT: 0x00000000
>             DSPACNTR: 0x98000000 (enabled, pipe A)
>           DSPASTRIDE: 0x00002000 (8192 bytes)
>              DSPAPOS: 0x00000000 (0, 0)
>             DSPASIZE: 0x02ff03ff (1024, 768)
>             DSPABASE: 0x04000000
>             DSPASURF: 0x00000000
>          DSPATILEOFF: 0x00000000
>            PIPEACONF: 0x80000000 (enabled, single-wide)
>             PIPEASRC: 0x03ff02ff (1024, 768)
>            PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS
> SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>    PIPEA_GMCH_DATA_M: 0x00000000
>    PIPEA_GMCH_DATA_N: 0x00000000
>      PIPEA_DP_LINK_M: 0x00000000
>      PIPEA_DP_LINK_N: 0x00000000
>        CURSOR_A_BASE: 0x34d6c000
>     CURSOR_A_CONTROL: 0x04000027
>    CURSOR_A_POSITION: 0x00180050
>                 FPA0: 0x00051610 (n = 5, m1 = 22, m2 = 16)
>                 FPA1: 0x00051610 (n = 5, m1 = 22, m2 = 16)
>               DPLL_A: 0x90810000 (enabled, non-dvo, default clock,
> DAC/serial mode, p1 = 3, p2 = 4)
>            DPLL_A_MD: 0x00000000
>             HTOTAL_A: 0x051f03ff (1024 active, 1312 total)
>             HBLANK_A: 0x051f03ff (1024 start, 1312 end)
>              HSYNC_A: 0x046f040f (1040 start, 1136 end)
>             VTOTAL_A: 0x031f02ff (768 active, 800 total)
>             VBLANK_A: 0x031f02ff (768 start, 800 end)
>              VSYNC_A: 0x03030300 (769 start, 772 end)
>            BCLRPAT_A: 0x00000000
>         VSYNCSHIFT_A: 0x00000000
>             DSPBCNTR: 0x99000000 (enabled, pipe B)
>           DSPBSTRIDE: 0x00002000 (8192 bytes)
>              DSPBPOS: 0x00000000 (0, 0)
>             DSPBSIZE: 0x0257031f (800, 600)
>             DSPBBASE: 0x04001000
>             DSPBSURF: 0x00000000
>          DSPBTILEOFF: 0x00000000
>            PIPEBCONF: 0x80000000 (enabled, single-wide)
>             PIPEBSRC: 0x031f0257 (800, 600)
>            PIPEBSTAT: 0x10000206 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS
> SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>    PIPEB_GMCH_DATA_M: 0x00000000
>    PIPEB_GMCH_DATA_N: 0x00000000
>      PIPEB_DP_LINK_M: 0x00000000
>      PIPEB_DP_LINK_N: 0x00000000
>        CURSOR_B_BASE: 0x00000000
>     CURSOR_B_CONTROL: 0x10000000
>    CURSOR_B_POSITION: 0x00180050
>                 FPB0: 0x0002130d (n = 2, m1 = 19, m2 = 13)
>                 FPB1: 0x0002130d (n = 2, m1 = 19, m2 = 13)
>               DPLL_B: 0xd0870000 (enabled, dvo, default clock, DAC/serial
> mode, p1 = 9, p2 = 4)
>            DPLL_B_MD: 0x00000000
>             HTOTAL_B: 0x041f031f (800 active, 1056 total)
>             HBLANK_B: 0x041f031f (800 start, 1056 end)
>              HSYNC_B: 0x03c70347 (840 start, 968 end)
>             VTOTAL_B: 0x02730257 (600 active, 628 total)
>             VBLANK_B: 0x02730257 (600 start, 628 end)
>              VSYNC_B: 0x025c0258 (601 start, 605 end)
>            BCLRPAT_B: 0x00000000
>         VSYNCSHIFT_B: 0x00000000
>    VCLK_DIVISOR_VGA0: 0x00021207
>    VCLK_DIVISOR_VGA1: 0x00031406
>        VCLK_POST_DIV: 0x0000888b
>             VGACNTRL: 0x80000000 (disabled)
>               TV_CTL: 0x00000000
>               TV_DAC: 0x00000000
>             TV_CSC_Y: 0x00000000
>            TV_CSC_Y2: 0x00000000
>             TV_CSC_U: 0x00000000
>            TV_CSC_U2: 0x00000000
>             TV_CSC_V: 0x00000000
>            TV_CSC_V2: 0x00000000
>         TV_CLR_KNOBS: 0x00000000
>         TV_CLR_LEVEL: 0x00000000
>           TV_H_CTL_1: 0x00000000
>           TV_H_CTL_2: 0x00000000
>           TV_H_CTL_3: 0x00000000
>           TV_V_CTL_1: 0x00000000
>           TV_V_CTL_2: 0x00000000
>           TV_V_CTL_3: 0x00000000
>           TV_V_CTL_4: 0x00000000
>           TV_V_CTL_5: 0x00000000
>           TV_V_CTL_6: 0x00000000
>           TV_V_CTL_7: 0x00000000
>          TV_SC_CTL_1: 0x00000000
>          TV_SC_CTL_2: 0x00000000
>          TV_SC_CTL_3: 0x00000000
>           TV_WIN_POS: 0x00000000
>          TV_WIN_SIZE: 0x00000000
>      TV_FILTER_CTL_1: 0x00000000
>      TV_FILTER_CTL_2: 0x00000000
>      TV_FILTER_CTL_3: 0x00000000
>        TV_CC_CONTROL: 0x00000000
>           TV_CC_DATA: 0x00000000
>          TV_H_LUMA_0: 0x00000000
>         TV_H_LUMA_59: 0x00000000
>        TV_H_CHROMA_0: 0x00000000
>       TV_H_CHROMA_59: 0x00000000
>         FBC_CFB_BASE: 0x00000000
>          FBC_LL_BASE: 0x00000000
>          FBC_CONTROL: 0x00000000
>          FBC_COMMAND: 0x00000000
>           FBC_STATUS: 0x00000000
>         FBC_CONTROL2: 0x00000000
>        FBC_FENCE_OFF: 0x00000000
>          FBC_MOD_NUM: 0x00000000
>              MI_MODE: 0x00000000
>         MI_ARB_STATE: 0x00000000
>       MI_RDRET_STATE: 0x00000000
>              ECOSKPD: 0x00000307
>                 DP_B: 0x00000000
>       DPB_AUX_CH_CTL: 0x00000000
>     DPB_AUX_CH_DATA1: 0x00000000
>     DPB_AUX_CH_DATA2: 0x00000000
>     DPB_AUX_CH_DATA3: 0x00000000
>     DPB_AUX_CH_DATA4: 0x00000000
>     DPB_AUX_CH_DATA5: 0x00000000
>                 DP_C: 0x00000000
>       DPC_AUX_CH_CTL: 0x00000000
>     DPC_AUX_CH_DATA1: 0x00000000
>     DPC_AUX_CH_DATA2: 0x00000000
>     DPC_AUX_CH_DATA3: 0x00000000
>     DPC_AUX_CH_DATA4: 0x00000000
>     DPC_AUX_CH_DATA5: 0x00000000
>                 DP_D: 0x00000000
>       DPD_AUX_CH_CTL: 0x00000000
>     DPD_AUX_CH_DATA1: 0x00000000
>     DPD_AUX_CH_DATA2: 0x00000000
>     DPD_AUX_CH_DATA3: 0x00000000
>     DPD_AUX_CH_DATA4: 0x00000000
>     DPD_AUX_CH_DATA5: 0x00000000
>           AUD_CONFIG: 0x00000000
>     AUD_HDMIW_STATUS: 0x00000000
>       AUD_CONV_CHCNT: 0x00000000
>        VIDEO_DIP_CTL: 0x00000000
>        AUD_PINW_CNTR: 0x00000000
>          AUD_CNTL_ST: 0x00000000
>          AUD_PIN_CAP: 0x00000000
>         AUD_PINW_CAP: 0x00000000
>   AUD_PINW_UNSOLRESP: 0x00000000
>     AUD_OUT_DIG_CNVT: 0x00000000
>        AUD_OUT_CWCAP: 0x00000000
>          AUD_GRP_CAP: 0x00000000
>             FENCE  0: 0x04000561 (enabled, X tiled, 32768 pitch, 0x04000000
> - 0x06000000 (32768kb))
>             FENCE  1: 0x01000561 (enabled, X tiled, 32768 pitch, 0x01000000
> - 0x03000000 (32768kb))
>             FENCE  2: 0x00000000 (disabled)
>             FENCE  3: 0x00000000 (disabled)
>             FENCE  4: 0x03500131 (enabled, X tiled, 4096 pitch, 0x03500000 -
> 0x03700000 (2048kb))
>             FENCE  5: 0x00000000 (disabled)
>             FENCE  6: 0x00000000 (disabled)
>             FENCE  7: 0x00000000 (disabled)
>             FENCE  8: 0x00000000 (disabled)
>             FENCE  9: 0x00000000 (disabled)
>            FENCE  10: 0x00000000 (disabled)
>            FENCE  11: 0x00000000 (disabled)
>            FENCE  12: 0x00000048 (disabled)
>            FENCE  13: 0x00000002 (disabled)
>            FENCE  14: 0x00000000 (disabled)
>            FENCE  15: 0x00000000 (disabled)
>        FENCE START 0: 0x00000000 (disabled)
>          FENCE END 0: 0x00000000 (disabled)
>        FENCE START 1: 0x00000000 (disabled)
>          FENCE END 1: 0x00000000 (disabled)
>        FENCE START 2: 0x00000048 (disabled)
>          FENCE END 2: 0x00000002 (disabled)
>        FENCE START 3: 0x00000000 (disabled)
>          FENCE END 3: 0x00000000 (disabled)
>        FENCE START 4: 0x00000000 (disabled)
>          FENCE END 4: 0x00000000 (disabled)
>        FENCE START 5: 0x00000000 (disabled)
>          FENCE END 5: 0x00000000 (disabled)
>        FENCE START 6: 0x00000000 (disabled)
>          FENCE END 6: 0x00000000 (disabled)
>        FENCE START 7: 0x00000000 (disabled)
>          FENCE END 7: 0x00000000 (disabled)
>        FENCE START 8: 0x00000000 (disabled)
>          FENCE END 8: 0x00000000 (disabled)
>        FENCE START 9: 0x00000000 (disabled)
>          FENCE END 9: 0x00000000 (disabled)
>       FENCE START 10: 0x00000000 (disabled)
>         FENCE END 10: 0x00000000 (disabled)
>       FENCE START 11: 0x00000000 (disabled)
>         FENCE END 11: 0x00000000 (disabled)
>       FENCE START 12: 0x00000000 (disabled)
>         FENCE END 12: 0x00000000 (disabled)
>       FENCE START 13: 0x00000000 (disabled)
>         FENCE END 13: 0x00000000 (disabled)
>       FENCE START 14: 0x00000000 (disabled)
>         FENCE END 14: 0x00000000 (disabled)
>       FENCE START 15: 0x00000000 (disabled)
>         FENCE END 15: 0x00000000 (disabled)
>              INST_PM: 0x00000000
> pipe A dot 78857 n 5 m1 22 m2 16 p1 3 p2 4
> pipe B dot 40000 n 2 m1 19 m2 13 p1 9 p2 4
> 
> Greetings,
>     Thomas
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



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