[Intel-gfx] Breaking suspend/resume by the Pipe A quirk

[Chris Wilson]

On Tue, Jun 03, 2014 at 05:50:06PM +0200, Thomas Richter wrote:
> Am 03.06.2014 17:26, schrieb Chris Wilson:
> 
> >
> >I should have said VGA. Thinking about it, it is likely a shared DDC line
> >so that only a single EDID can be read.
> 
> Actually, it gets the EDID from the VGA panel just fine, also shows
> me the modes it supports. DVI1 has no edit, though it gets its
> allowable modes from the dvo_ds2501 module.
> 
> I now tried to relocate VGA1 to crtc 1, with Daniel's patch. Results
> are even weirder. I can *set* the resolution to 1280x1024 on VGA1,
> just that it does not deliver this resolution. My monitor claims
> (and my vision confirms) that this is still the same 1024x768 mode
> as on the internal panel.
> 
> I can again turn VGA off, relocate it to crtc 1, turn it on again,
> still says its a clone of DVI1 even though it's on a different crtc.
> 
> Chipset (lspci) says its a 82830M/MG graphics controller, PCI id
> 8086:3577. This *should* be a true 830MG (specs agree), thus I
> *believe* it should have two display pipes. The R31 is built around
> the very same chipset and has no problems with independent output.
> Looks like they shared the VGA and DVI output,and left the other
> output just dangling. Weird.
> 
> Screen 0: minimum 320 x 200, current 1280 x 1024, maximum 2048 x 2048
> VGA1 connected 1280x1024+0+0 (0xa7) normal (normal left inverted
> right x axis y axis) 338mm x 270mm
> 	Identifier: 0x41
> 	Timestamp:  504191
> 	Subpixel:   unknown
> 	Gamma:      1.0:1.0:1.0
> 	Brightness: 1.0
> 	Clones:     DVI1
        ^^^^^^^^^^^^^^^^^

This is short for "Allowed Clones:", not "Active Clones:".

>   1280x1024 (0xa7)  108.0MHz +HSync +VSync *current +preferred
>         h: width  1280 start 1328 end 1440 total 1688 skew    0
> clock  64.0KHz
>         v: height 1024 start 1025 end 1028 total 1066
> clock  60.0Hz

>             DSPBCNTR: 0x99000000 (enabled, pipe B)
>           DSPBSTRIDE: 0x00002000 (8192 bytes)
>              DSPBPOS: 0x00000000 (0, 0)
>             DSPBSIZE: 0x0257031f (800, 600)
>             DSPBBASE: 0x04001000
>             DSPBSURF: 0x00000000
>          DSPBTILEOFF: 0x00000000
>            PIPEBCONF: 0x80000000 (enabled, single-wide)
>             PIPEBSRC: 0x031f0257 (800, 600)
>            PIPEBSTAT: 0x10000206 (status: CRC_DONE_ENABLE
>             HTOTAL_B: 0x041f031f (800 active, 1056 total)
>             HBLANK_B: 0x041f031f (800 start, 1056 end)
>              HSYNC_B: 0x03c70347 (840 start, 968 end)
>             VTOTAL_B: 0x02730257 (600 active, 628 total)
>             VBLANK_B: 0x02730257 (600 start, 628 end)
>              VSYNC_B: 0x025c0258 (601 start, 605 end)

It's even worse than you thought. Somewhere between userspace passing in
the mode, and the kernel setting it, it got lost.

> 	CRTC:       1
> 	CRTCs:      0 1
> 	Transform:  1.000000 0.000000 0.000000
> 	            0.000000 1.000000 0.000000
> 	            0.000000 0.000000 1.000000
> 	           filter:
>   1280x1024 (0xa7)  108.0MHz +HSync +VSync *current +preferred
>         h: width  1280 start 1328 end 1440 total 1688 skew    0
> clock  64.0KHz
>         v: height 1024 start 1025 end 1028 total 1066

> DVI1 connected 1280x1024+0+0 (0x43) normal (normal left inverted
                 ^^^^^^^^^^^^^

This means you have configured the two outputs in a mirrored mode, both
reading from the same portion of the framebuffer. So it just looks like
a cloned setup, with upset displays.

> right x axis y axis) 0mm x 0mm panning 1280x1024+0+0
> 	Identifier: 0x42
> 	Timestamp:  504191
> 	Subpixel:   horizontal rgb
> 	Gamma:      1.0:1.0:1.0
> 	Brightness: 1.0
> 	Clones:     VGA1
> 	CRTC:       0
> 	CRTCs:      0 1
> 	Panning:    1280x1024+0+0
> 	Tracking:   0x0+0+0
> 	Border:     0/0/0/0
> 	Transform:  1.000000 0.000000 0.000000
> 	            0.000000 1.000000 0.000000
> 	            0.000000 0.000000 1.000000
> 	           filter:
>   1024x768 (0x43)   65.0MHz -HSync -VSync *current
>         h: width  1024 start 1048 end 1184 total 1344 skew    0
> clock  48.4KHz
>         v: height  768 start  771 end  777 total  806
>            PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE

>             DSPACNTR: 0x98000000 (enabled, pipe A)
>           DSPASTRIDE: 0x00002000 (8192 bytes)
>              DSPAPOS: 0x00000000 (0, 0)
>             DSPASIZE: 0x02ff03ff (1024, 768)
>             DSPABASE: 0x04000000
>             DSPASURF: 0x00000000
>          DSPATILEOFF: 0x00000000
>            PIPEACONF: 0x80000000 (enabled, single-wide)
>             PIPEASRC: 0x03ff02ff (1024, 768)
>             HTOTAL_A: 0x051f03ff (1024 active, 1312 total)
>             HBLANK_A: 0x051f03ff (1024 start, 1312 end)
>              HSYNC_A: 0x046f040f (1040 start, 1136 end)
>             VTOTAL_A: 0x031f02ff (768 active, 800 total)
>             VBLANK_A: 0x031f02ff (768 start, 800 end)
>              VSYNC_A: 0x03030300 (769 start, 772 end)

At least this is sane.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre