[Intel-gfx] [PATCH] drm/i915/bdw: Add Broadwell support for debugfs rps freq info

[Daniel Vetter]

On Fri, May 30, 2014 at 04:22:10PM -0700, Tom.O'Rourke at intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke at intel.com>
> 
> Add Broadwell support to i915_frequency_info
> and extend i915_max|min_freq_get|set to (gen >= 6).
> 
> v2: generalized support for i915_max|min_freq_get|set (Daniel).
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |   16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5858cbb..a75d57d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1027,7 +1027,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  			   MEMSTAT_VID_SHIFT);
>  		seq_printf(m, "Current P-state: %d\n",
>  			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
> -	} else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
> +	} else if (IS_GEN6(dev)
> +			|| (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
> +			|| IS_BROADWELL(dev)) {

Nitpick: This isn't how CodingStyle recommends to break multi-line if
statements. And as far as if checks go, this is horrible ;-)

But the other stuff is much prettier, so I've gone ahead and merged this.
-Daniel

>  		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
>  		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
>  		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> @@ -1046,7 +1048,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  
>  		reqf = I915_READ(GEN6_RPNSWREQ);
>  		reqf &= ~GEN6_TURBO_DISABLE;
> -		if (IS_HASWELL(dev))
> +		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			reqf >>= 24;
>  		else
>  			reqf >>= 25;
> @@ -1063,7 +1065,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>  		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
>  		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
>  		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
> -		if (IS_HASWELL(dev))
> +		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
>  		else
>  			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> @@ -3500,7 +3502,7 @@ i915_max_freq_get(void *data, u64 *val)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int ret;
>  
> -	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
> +	if (INTEL_INFO(dev)->gen < 6)
>  		return -ENODEV;
>  
>  	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> @@ -3526,7 +3528,7 @@ i915_max_freq_set(void *data, u64 val)
>  	u32 rp_state_cap, hw_max, hw_min;
>  	int ret;
>  
> -	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
> +	if (INTEL_INFO(dev)->gen < 6)
>  		return -ENODEV;
>  
>  	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> @@ -3581,7 +3583,7 @@ i915_min_freq_get(void *data, u64 *val)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	int ret;
>  
> -	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
> +	if (INTEL_INFO(dev)->gen < 6)
>  		return -ENODEV;
>  
>  	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> @@ -3607,7 +3609,7 @@ i915_min_freq_set(void *data, u64 val)
>  	u32 rp_state_cap, hw_max, hw_min;
>  	int ret;
>  
> -	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
> +	if (INTEL_INFO(dev)->gen < 6)
>  		return -ENODEV;
>  
>  	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> -- 
> 1.7.9.5
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch