[Intel-gfx] [PATCH 0/2] Enabling D0i3 transition for Valleyview

[sagar.a.kamble at intel.com]

From: Sagar Kamble <sagar.a.kamble at intel.com>

With these patches runtime_suspend is triggered by updating runtime pm
usage count when display well is power gated and pci state is set to D3 hot
in runtime_suspend and set to D0 in runtime_resume.

Sagar Kamble (2):
  drm/i915: do runtime_get/put during display well power gate/ungate
  drm/i915/vlv: Set D3_hot for vlv during runtime_suspend

 drivers/gpu/drm/i915/i915_drv.c | 11 +++++++++++
 drivers/gpu/drm/i915/intel_pm.c |  6 ++++++
 2 files changed, 17 insertions(+)

-- 
1.8.5