[Intel-gfx] [PATCH] drm/i915/bdw: Do not write the Semaphore Sync Registers in GEN8+

[Daniel Vetter]

On Wed, Jun 11, 2014 at 04:17:16PM +0100, oscar.mateo at intel.com wrote:
> From: Oscar Mateo <oscar.mateo at intel.com>
> 
> These do not exist anymore.
> 
> Spotted while reading through intel_ringbuffer.c
> 
> Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 279488a..0eaaaec 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1746,14 +1746,15 @@ int intel_ring_cacheline_align(struct intel_engine_cs *ring)
>  
>  void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
>  {
> -	struct drm_i915_private *dev_priv = ring->dev->dev_private;
> +	struct drm_device *dev = ring->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	BUG_ON(ring->outstanding_lazy_seqno);
>  
> -	if (INTEL_INFO(ring->dev)->gen >= 6) {
> +	if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
>  		I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
>  		I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
> -		if (HAS_VEBOX(ring->dev))
> +		if (HAS_VEBOX(dev))
>  			I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
>  	}
>  
> -- 
> 1.9.0
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch