[Intel-gfx] [PATCH] drm/i915: re-order ppgtt sanitize logic v2

[Jesse Barnes]

Put hw limitations first, disabling ppgtt if necessary right away.
After that, check user passed args or auto-detect and do the right
thing, falling back to aliasing PPGTT if the user tries to enable full
PPGTT but it isn't available.

v2: simplify auto-detect case since we already caught the no PPGTT case early
    on (Jesse)

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c |   25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d45303d..26145ad 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -35,15 +35,6 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
 
 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 {
-	if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
-		return 0;
-
-	if (enable_ppgtt == 1)
-		return 1;
-
-	if (enable_ppgtt == 2 && HAS_PPGTT(dev))
-		return 2;
-
 #ifdef CONFIG_INTEL_IOMMU
 	/* Disable ppgtt on SNB if VT-d is on. */
 	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
@@ -56,10 +47,20 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 	if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xc)
 		return 0;
 
-	if (HAS_PPGTT(dev))
-		return 2;
+	if (!HAS_ALIASING_PPGTT(dev))
+		return 0;
 
-	return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
+	/* Check user passed enable_ppgtt param and try to honor it */
+	switch (enable_ppgtt) {
+	case 0:
+		return 0;
+	case 1:
+		return 1; /* caught any hw limits above */
+	case 2:
+		/* fall through to auto-detect */
+	default: /* auto-detect */
+		return HAS_PPGTT(dev) ? 2 : 1;
+	}
 }
 
 
-- 
1.7.9.5