[Intel-gfx] [PATCH 37/53] drm/i915/bdw: Implement context switching (somewhat)

[Chris Wilson]

On Fri, Jun 13, 2014 at 04:37:55PM +0100, oscar.mateo at intel.com wrote:
> +static void execlists_elsp_write(struct intel_engine_cs *ring,
> +				 struct drm_i915_gem_object *ctx_obj0,
> +				 struct drm_i915_gem_object *ctx_obj1)
> +{
> +	struct drm_i915_private *dev_priv = ring->dev->dev_private;
> +	uint64_t temp = 0;
> +	uint32_t desc[4];
> +
> +	/* XXX: You must always write both descriptors in the order below. */
> +	if (ctx_obj1)
> +		temp = execlists_ctx_descriptor(ctx_obj1);
> +	else
> +		temp = 0;
> +	desc[1] = (u32)(temp >> 32);
> +	desc[0] = (u32)temp;
> +
> +	temp = execlists_ctx_descriptor(ctx_obj0);
> +	desc[3] = (u32)(temp >> 32);
> +	desc[2] = (u32)temp;
> +
> +	/* Set Force Wakeup bit to prevent GT from entering C6 while
> +	 * ELSP writes are in progress */
> +	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
> +
> +	I915_WRITE(RING_ELSP(ring), desc[1]);
> +	I915_WRITE(RING_ELSP(ring), desc[0]);
> +	I915_WRITE(RING_ELSP(ring), desc[3]);
> +	/* The context is automatically loaded after the following */
> +	I915_WRITE(RING_ELSP(ring), desc[2]);
> +
> +	/* ELSP is a write only register, so this serves as a posting read */

I can see that is a POSTING_READ, so say something like
/* ELSP is a wo reg, so use another nearby reg for posting instead */

> +	POSTING_READ(RING_EXECLIST_STATUS(ring));
> +
> +	/* Release Force Wakeup */

Redundant, the clue is in the function name.

> +	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
> +}
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre