[Intel-gfx] [PATCH 1/4] drm/i915: Ack interrupts before handling them (GEN5 - GEN7)

[Chris Wilson]

On Mon, Jun 16, 2014 at 12:30:26PM +0100, oscar.mateo at intel.com wrote:
> From: Oscar Mateo <oscar.mateo at intel.com>
> 
> Otherwise, we might receive a new interrupt before we have time to ack the first
> one, eventually missing it.

Without a atomic xchg operation with mmio space, we merely reduce the
window. This is even more apparent when you consider how heavyweight
those I915_READ/I915_WRITE are.

> According to BSPec, the right order should be:
> 
> 1 - Disable Master Interrupt Control.
> 2 - Find the source(s) of the interrupt and clear the Interrupt Identity bits (IIR)
> 4 - Process the interrupt(s) that had bits set in the IIRs.
> 5 - Re-enable Master Interrupt Control.
> 
> We maintain the "disable SDE interrupts when handling" hack since apparently it works.
> 
> Spotted by Bob Beckett <robert.beckett at intel.com>.
> 
> Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>

I'd like the changelog slightly clarified, and the notes here would be
useful in the code as well to describe the theory of operation in
handling IRQ.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre