[Intel-gfx] [PATCH 1/2] drm/i915: update BDW DDI buffer translations
Daniel Vetter
daniel at ffwll.ch
Mon Jun 16 19:58:00 CEST 2014
On Sat, Jun 14, 2014 at 10:11:51AM +0100, Damien Lespiau wrote:
> On Fri, Jun 13, 2014 at 06:45:40PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> >
> > Two BSpec updates changed the recommended values for BDW eDP and DP
> > DDI buffer translations. Now the signal levels also match the HSW signal
> > levels, which simplify things a little bit.
> >
> > It seems some DP sinks don't work properly without voltage level 0 and
> > pre-emphasis level 3, so this patch may fix some bugs on
> > panels/monitors that happen on BDW but not on HSW.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
Both merged to dinq. We can always apply this to -fixes once we have
confirmation that it actually fixes something seen in the wild.
-Daniel
>
> --
> Damien
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 11 --------
> > drivers/gpu/drm/i915/intel_ddi.c | 4 +--
> > drivers/gpu/drm/i915/intel_dp.c | 55 +++-------------------------------------
> > 3 files changed, 5 insertions(+), 65 deletions(-)
> >
> > This doesn't fix the "eDP 5GHz 2 lanes doesn't work" bug I can reproduce on my
> > machine if I revert the upstream hack we currently have.
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 9ce017b..e1fb0f2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5821,7 +5821,6 @@ enum punit_power_well {
> > #define DDI_BUF_CTL_B 0x64100
> > #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
> > #define DDI_BUF_CTL_ENABLE (1<<31)
> > -/* Haswell */
> > #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
> > #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
> > #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
> > @@ -5831,16 +5830,6 @@ enum punit_power_well {
> > #define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
> > #define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
> > #define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
> > -/* Broadwell */
> > -#define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */
> > -#define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */
> > -#define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */
> > -#define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */
> > -#define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */
> > -#define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */
> > -#define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */
> > -#define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */
> > -#define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */
> > #define DDI_BUF_EMP_MASK (0xf<<24)
> > #define DDI_BUF_PORT_REVERSAL (1<<16)
> > #define DDI_BUF_IS_IDLE (1<<7)
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index b17b9c7..ded6013 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -76,12 +76,12 @@ static const u32 bdw_ddi_translations_edp[] = {
> > 0x00FFFFFF, 0x00000012, /* eDP parameters */
> > 0x00EBAFFF, 0x00020011,
> > 0x00C71FFF, 0x0006000F,
> > + 0x00AAAFFF, 0x000E000A,
> > 0x00FFFFFF, 0x00020011,
> > 0x00DB6FFF, 0x0005000F,
> > 0x00BEEFFF, 0x000A000C,
> > 0x00FFFFFF, 0x0005000F,
> > 0x00DB6FFF, 0x000A000C,
> > - 0x00FFFFFF, 0x000A000C,
> > 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
> > };
> >
> > @@ -89,12 +89,12 @@ static const u32 bdw_ddi_translations_dp[] = {
> > 0x00FFFFFF, 0x0007000E, /* DP parameters */
> > 0x00D75FFF, 0x000E000A,
> > 0x00BEFFFF, 0x00140006,
> > + 0x80B2CFFF, 0x001B0002,
> > 0x00FFFFFF, 0x000E000A,
> > 0x00D75FFF, 0x00180004,
> > 0x80CB2FFF, 0x001B0002,
> > 0x00F7DFFF, 0x00180004,
> > 0x80D75FFF, 0x001B0002,
> > - 0x80FFFFFF, 0x001B0002,
> > 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index b6b2640..dc58044 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -2330,7 +2330,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > enum port port = dp_to_dig_port(intel_dp)->port;
> >
> > - if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
> > + if (IS_VALLEYVIEW(dev))
> > return DP_TRAIN_VOLTAGE_SWING_1200;
> > else if (IS_GEN7(dev) && port == PORT_A)
> > return DP_TRAIN_VOLTAGE_SWING_800;
> > @@ -2346,18 +2346,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> > struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > enum port port = dp_to_dig_port(intel_dp)->port;
> >
> > - if (IS_BROADWELL(dev)) {
> > - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> > - case DP_TRAIN_VOLTAGE_SWING_400:
> > - case DP_TRAIN_VOLTAGE_SWING_600:
> > - return DP_TRAIN_PRE_EMPHASIS_6;
> > - case DP_TRAIN_VOLTAGE_SWING_800:
> > - return DP_TRAIN_PRE_EMPHASIS_3_5;
> > - case DP_TRAIN_VOLTAGE_SWING_1200:
> > - default:
> > - return DP_TRAIN_PRE_EMPHASIS_0;
> > - }
> > - } else if (IS_HASWELL(dev)) {
> > + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> > switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> > case DP_TRAIN_VOLTAGE_SWING_400:
> > return DP_TRAIN_PRE_EMPHASIS_9_5;
> > @@ -2829,41 +2818,6 @@ intel_hsw_signal_levels(uint8_t train_set)
> > }
> > }
> >
> > -static uint32_t
> > -intel_bdw_signal_levels(uint8_t train_set)
> > -{
> > - int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> > - DP_TRAIN_PRE_EMPHASIS_MASK);
> > - switch (signal_levels) {
> > - case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
> > - return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
> > - case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
> > - return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
> > - case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
> > - return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
> > -
> > - case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
> > - return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
> > - case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
> > - return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
> > - case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
> > - return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
> > -
> > - case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
> > - return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
> > - case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
> > - return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
> > -
> > - case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
> > - return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
> > -
> > - default:
> > - DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
> > - "0x%x\n", signal_levels);
> > - return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
> > - }
> > -}
> > -
> > /* Properly updates "DP" with the correct signal levels. */
> > static void
> > intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
> > @@ -2874,10 +2828,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
> > uint32_t signal_levels, mask;
> > uint8_t train_set = intel_dp->train_set[0];
> >
> > - if (IS_BROADWELL(dev)) {
> > - signal_levels = intel_bdw_signal_levels(train_set);
> > - mask = DDI_BUF_EMP_MASK;
> > - } else if (IS_HASWELL(dev)) {
> > + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> > signal_levels = intel_hsw_signal_levels(train_set);
> > mask = DDI_BUF_EMP_MASK;
> > } else if (IS_CHERRYVIEW(dev)) {
> > --
> > 2.0.0
> >
> > _______________________________________________
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> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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