[Intel-gfx] [PATCH 2/3] drm/i915: Add 180 degree primary plane rotation support
Jindal, Sonika
sonika.jindal at intel.com
Tue Jun 24 12:34:07 CEST 2014
On 6/24/2014 3:59 PM, Damien Lespiau wrote:
> On Mon, Jun 23, 2014 at 11:06:00AM +0530, sonika.jindal at intel.com wrote:
>> From: Sonika Jindal <sonika.jindal at intel.com>
>>
>> Primary planes support 180 degree rotation. Expose the feature
>> through rotation drm property.
>>
>> v2: Calculating linear/tiled offsets based on pipe source width and
>> height. Added 180 degree rotation support in ironlake_update_plane.
>>
>> v3: Checking if CRTC is active before issueing update_plane. Added
>> wait for vblank to make sure we dont overtake page flips. Disabling
>> FBC since it does not work with rotated planes.
>>
>> v4: Updated rotation checks for pending flips, fbc disable. Creating
>> rotation property only for Gen4 onwards. Property resetting as part
>> of lastclose.
>>
>> v5: Resetting property in i915_driver_lastclose properly for planes
>> and crtcs. Fixed linear offset calculation that was off by 1 w.r.t
>> width in i9xx_update_plane and ironlake_update_plane. Removed tab
>> based indentation and unnecessary braces in intel_crtc_set_property
>> and intel_update_fbc. FBC and flip related checks should be done only
>> for valid crtcs.
>>
>> v6: Minor nits in FBC disable checks for comments in intel_crtc_set_property
>> and positioning the disable code in intel_update_fbc.
>>
>> v7: In case rotation property on inactive crtc is updated, we return
>> successfully printing debug log as crtc is inactive and only property change
>> is preserved.
>>
>> v8: update_plane is changed to update_primary_plane, crtc->fb is changed to
>> crtc->primary->fb and return value of update_primary_plane is ignored.
>>
>> v9: added rotation property to primary plane instead of crtc. Removing reset
>> of rotation property from lastclose. rotation_property is moved to drm_plane,so
>> drm layer will take care of resetting.
>>
>> Testcase: igt/kms_rotation_crc
>>
>> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
>> Cc: Jani Nikula <jani.nikula at linux.intel.com>
>> Cc: dri-devel at lists.freedesktop.org
>> Cc: vijay.a.purushothaman at intel.com
>> Signed-off-by: Uma Shankar <uma.shankar at intel.com>
>> Signed-off-by: Sagar Kamble <sagar.a.kamble at intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_dma.c | 5 --
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_display.c | 94 ++++++++++++++++++++++++++++++++--
>> drivers/gpu/drm/i915/intel_pm.c | 8 +++
>> 4 files changed, 98 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>> index 5e583a1..4b6b911 100644
>> --- a/drivers/gpu/drm/i915/i915_dma.c
>> +++ b/drivers/gpu/drm/i915/i915_dma.c
>> @@ -1938,14 +1938,9 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file)
>> */
>> void i915_driver_lastclose(struct drm_device *dev)
>> {
>> - struct drm_i915_private *dev_priv = dev->dev_private;
>> -
>> /* On gen6+ we refuse to init without kms enabled, but then the drm core
>> * goes right around and calls lastclose. Check for this and don't clean
>> * up anything. */
>> - if (!dev_priv)
>> - return;
>> -
>> if (drm_core_check_feature(dev, DRIVER_MODESET)) {
>> intel_fbdev_restore_mode(dev);
>> vga_switcheroo_process_delayed_switch();
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c70c804..c600d3b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4087,6 +4087,7 @@ enum punit_power_well {
>> #define DISPPLANE_NO_LINE_DOUBLE 0
>> #define DISPPLANE_STEREO_POLARITY_FIRST 0
>> #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
>> +#define DISPPLANE_ROTATE_180 (1<<15)
>> #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
>> #define DISPPLANE_TILED (1<<10)
>> #define _DSPAADDR 0x70184
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 5e8e711..85bd3b8 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2414,7 +2414,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>> unsigned long linear_offset;
>> u32 dspcntr;
>> u32 reg;
>> + int pixel_size;
>>
>> + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
>> intel_fb = to_intel_framebuffer(fb);
>> obj = intel_fb->obj;
>>
>> @@ -2422,6 +2424,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>> dspcntr = I915_READ(reg);
>> /* Mask out pixel format bits in case we change it */
>> dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
>> + dspcntr &= ~DISPPLANE_ROTATE_180;
>> +
>> switch (fb->pixel_format) {
>> case DRM_FORMAT_C8:
>> dspcntr |= DISPPLANE_8BPP;
>> @@ -2463,8 +2467,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>> if (IS_G4X(dev))
>> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>>
>> - I915_WRITE(reg, dspcntr);
>> -
>> linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
>>
>> if (INTEL_INFO(dev)->gen >= 4) {
>> @@ -2477,6 +2479,17 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>> intel_crtc->dspaddr_offset = linear_offset;
>> }
>>
>> + if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
>> + dspcntr |= DISPPLANE_ROTATE_180;
>> +
>> + x += (intel_crtc->config.pipe_src_w - 1);
>> + y += (intel_crtc->config.pipe_src_h - 1);
>> + linear_offset += (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
>> + (intel_crtc->config.pipe_src_w - 1) * pixel_size;
>> + }
>> +
>> + I915_WRITE(reg, dspcntr);
>> +
>> DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
>> i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
>> fb->pitches[0]);
>> @@ -2487,7 +2500,8 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
>> I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
>> I915_WRITE(DSPLINOFF(plane), linear_offset);
>> } else
>> - I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
>> + I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) +
>> + linear_offset);
>> POSTING_READ(reg);
>> }
>>
>> @@ -2504,7 +2518,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>> unsigned long linear_offset;
>> u32 dspcntr;
>> u32 reg;
>> + int pixel_size;
>>
>> + pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
>> intel_fb = to_intel_framebuffer(fb);
>> obj = intel_fb->obj;
>>
>> @@ -2512,6 +2528,8 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>> dspcntr = I915_READ(reg);
>> /* Mask out pixel format bits in case we change it */
>> dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
>> + dspcntr &= ~DISPPLANE_ROTATE_180;
>> +
>> switch (fb->pixel_format) {
>> case DRM_FORMAT_C8:
>> dspcntr |= DISPPLANE_8BPP;
>> @@ -2549,8 +2567,6 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>> else
>> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>>
>> - I915_WRITE(reg, dspcntr);
>> -
>> linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
>> intel_crtc->dspaddr_offset =
>> intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
>> @@ -2558,6 +2574,20 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
>> fb->pitches[0]);
>> linear_offset -= intel_crtc->dspaddr_offset;
>>
>> + if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
>> + dspcntr |= DISPPLANE_ROTATE_180;
>> +
>> + if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
>> + x += (intel_crtc->config.pipe_src_w - 1);
>> + y += (intel_crtc->config.pipe_src_h - 1);
>> + linear_offset += (intel_crtc->config.pipe_src_h - 1) *
>> + fb->pitches[0] + (intel_crtc->config.pipe_src_w - 1) *
>> + pixel_size;
>> + }
>> + }
>> +
>> + I915_WRITE(reg, dspcntr);
>> +
>> DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
>> i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
>> fb->pitches[0]);
>> @@ -11324,10 +11354,50 @@ static void intel_plane_destroy(struct drm_plane *plane)
>> kfree(intel_plane);
>> }
>>
>> +static int intel_primary_plane_set_property(struct drm_plane *plane,
>> + struct drm_property *prop,
>> + uint64_t val)
>> +{
>> + struct drm_device *dev = plane->dev;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + struct intel_plane *intel_plane = to_intel_plane(plane);
>> + struct intel_crtc *intel_crtc = to_intel_crtc(plane->crtc);
>> + struct drm_crtc *crtc = &intel_crtc->base;
>> + uint64_t old_val;
>> +
>> + if (prop == plane->rotation_property) {
>> + /* exactly one rotation angle please */
>> + if (hweight32(val & 0xf) != 1)
>> + return -EINVAL;
>> +
>> + old_val = intel_plane->rotation;
>> + intel_plane->rotation = val;
>> +
>> + if (intel_crtc->active && intel_crtc->primary_enabled) {
>> + intel_crtc_wait_for_pending_flips(crtc);
>> +
>> + /* FBC does not work on some platforms for rotated planes */
>> + if (dev_priv->fbc.plane == intel_crtc->plane &&
>> + INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
>> + intel_plane->rotation != BIT(DRM_ROTATE_0))
>> + intel_disable_fbc(dev);
>> + dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
>> + 0, 0);
>> +
>> + } else {
>> + DRM_DEBUG_KMS("[CRTC:%d] is not active. Only rotation property is updated\n",
>> + crtc->base.id);
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> static const struct drm_plane_funcs intel_primary_plane_funcs = {
>> .update_plane = intel_primary_plane_setplane,
>> .disable_plane = intel_primary_plane_disable,
>> .destroy = intel_plane_destroy,
>> + .set_property = intel_primary_plane_set_property
>> };
>>
>> static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
>> @@ -11335,6 +11405,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
>> {
>> struct intel_plane *primary;
>> const uint32_t *intel_primary_formats;
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> int num_formats;
>
> Here and elsewhere, you're adding dev_priv to remove it in the next
> patch. A left over from putting the rotation property in drm_plane.
>
Yes..I will remove it from here and resend the patches.
More information about the Intel-gfx
mailing list