[Intel-gfx] [PATCH 01/11] drm/i915: Set primary plane enable at dpcntrl.

Rodrigo Vivi rodrigo.vivi at gmail.com
Sat Mar 1 00:44:36 CET 2014


This patch allows system to safely recover after kms_psr_sink_crc check
or any other similar case that might fail when PSR is enabled.

Ville made and sent me this patch after noticing that primary plane enabled
bit was set during test case and unset after failure. What was causing a hard
and non-recoverable blank screen.

After the failure when alternating from fbcon to x section it was possible to
see and move mouse cursor, but nothing else. Everything else was fully black.
A for dpms off/on also haleped to get screen back. But this patch seeting
primary plane enabled bit propertly seemed more clean.

v2: Fix identation issue.
v3: Add the XXX comment.

Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e05d1e..e23ff4c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2118,6 +2118,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 	if (IS_G4X(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
+	if (intel_crtc->primary_enabled)
+		dspcntr |= DISPLAY_PLANE_ENABLE;
+
 	I915_WRITE(reg, dspcntr);
 
 	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
@@ -2215,6 +2218,9 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
 	else
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
+	if (intel_crtc->primary_enabled)
+		dspcntr |= DISPLAY_PLANE_ENABLE;
+
 	I915_WRITE(reg, dspcntr);
 
 	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
@@ -8633,6 +8639,13 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
 	intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
 	intel_ring_emit(ring, (MI_NOOP));
 
+	/* XXX: Ugly hack to avoid PSR test case eventually breaking things up
+	 * to be removed whenever it is fixed. */
+	if (IS_VALLEYVIEW(dev) && intel_crtc->primary_enabled)
+		I915_WRITE(DSPCNTR(intel_crtc->plane),
+			   I915_READ(DSPCNTR(intel_crtc->plane))
+			   | DISPLAY_PLANE_ENABLE);
+
 	intel_mark_page_flip_active(intel_crtc);
 	__intel_ring_advance(ring);
 	return 0;
-- 
1.8.3.1




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