[Intel-gfx] [PATCH 08/11] drm/i915: PSR Baytrail debugfs.

[Rodrigo Vivi]

Add debugfs support for Baytrail considering that on Baytrail we can
have PSR on pipe A or pipe B and we don't have any kind of
performance counter as we have on other platforms that support PSR.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 36 +++++++++++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d90a707..9d86808 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1900,6 +1900,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	struct drm_device *dev = node->minor->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 psrperf = 0;
+	u32 statA = 0;
+	u32 statB = 0;
 	bool enabled = false;
 
 	intel_runtime_pm_get(dev_priv);
@@ -1907,14 +1909,38 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
 	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
 
-	enabled = HAS_PSR(dev) &&
-		I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
-	seq_printf(m, "Enabled: %s\n", yesno(enabled));
+	if (HAS_PSR(dev)) {
+		if (IS_VALLEYVIEW(dev)) {
+			statA = I915_READ(VLV_PSRSTAT(PIPE_A)) &
+				VLV_EDP_PSR_CURR_STATE_MASK;
+			statB = I915_READ(VLV_PSRSTAT(PIPE_B)) &
+				VLV_EDP_PSR_CURR_STATE_MASK;
+			enabled = ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+				   (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE) ||
+				   (statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+				   (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE));
+		} else
+			enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
+	}
+	seq_printf(m, "Enabled: %s", yesno(enabled));
 
-	if (HAS_PSR(dev))
+	if (IS_VALLEYVIEW(dev)) {
+		if ((statA == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+		    (statA == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+			seq_puts(m, " pipe A");
+		if ((statB == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
+		    (statB == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
+			seq_puts(m, " pipe B");
+	}
+
+	seq_puts(m, "\n");
+
+	/* VLV PSR has no kind of performance counter */
+	if (HAS_PSR(dev) && !IS_VALLEYVIEW(dev)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
 			EDP_PSR_PERF_CNT_MASK;
-	seq_printf(m, "Performance_Counter: %u\n", psrperf);
+		seq_printf(m, "Performance_Counter: %u\n", psrperf);
+	}
 
 	intel_runtime_pm_put(dev_priv);
 	return 0;
-- 
1.8.3.1