[Intel-gfx] [PATCH] Revert "drm/i915: enable HiZ Raw Stall Optimization on IVB"

[Ville Syrjälä]

On Tue, Mar 04, 2014 at 10:38:58PM +0800, Chia-I Wu wrote:
> On Tue, Mar 4, 2014 at 5:41 PM, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> > This reverts commit 116f2b6da868dec7539103574d0421cd6221e931.
> >
> > This optimization causes widespread corruption in games, and even in
> > glxgears, on my ivb:gt1. The corruption appears like z-fighting of
> > overlapping polygons in the HiZ buffer.
> >
> > The observation ties in very closely with the description of the
> > optimization disabled by default on IVB:
> >
> > "The Hierarchical Z RAW Stall Optimization allows non-overlapping
> > polygons in the same 8x4 pixel/sample area to be processed without
> > stalling waiting for the earlier ones to write to Hierarchical Z
> > buffer."
> >
> > No reason is given for why it is disabled by default, usually for such
> > optimizations it is that it is incomplete. However, there is no
> > indication whether this a gt1 only issue either. Before considering
> > reenabling this optimization, I would first suggest reproducing the
> > corruption in piglit.
> I wonder if Haswell GT1 is affected too (that's in another commit).  I
> do not own a GT1 for either GEN to verify the issue or to create a
> sensible piglit test.

I'm seeing corruption on IVB GT2 as well. I might be more blind than
Chris or it's less subtle on GT2 since it took me a while to spot it.
Seems to be easiest to spot in Epic citadel when you go inside the
temple. I can't spot the same corruption on HSW GT3.

> 
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75623
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Chia-I Wu <olv at lunarg.com>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 8 +++++---
> >  1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index b016d9bcd7c1..6b4d1a89e9bc 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4908,9 +4908,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >
> >         gen7_setup_fixed_func_scheduler(dev_priv);
> >
> > -       /* enable HiZ Raw Stall Optimization */
> > -       I915_WRITE(CACHE_MODE_0_GEN7,
> > -                  _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> > +       if (0) { /* causes HiZ corruption on ivb:gt1 */
> > +               /* enable HiZ Raw Stall Optimization */
> > +               I915_WRITE(CACHE_MODE_0_GEN7,
> > +                          _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> > +       }
> >
> >         /* WaDisable4x2SubspanOptimization:ivb */
> >         I915_WRITE(CACHE_MODE_1,
> > --
> > 1.9.0
> >
> 
> 
> 
> -- 
> olv at LunarG.com

-- 
Ville Syrjälä
Intel OTC