[Intel-gfx] [PATCH] drm/i915: Revert workaround for disabling L3 cache aging on IVB

[Daniel Vetter]

On Mon, Feb 17, 2014 at 10:59:09AM +0200, Ville Syrjälä wrote:
> On Fri, Feb 14, 2014 at 10:34:43PM +0000, Chris Wilson wrote:
> > In commit e4e0c058a19c41150d12ad2d3023b3cf09c5de67
> > Author: Eugeni Dodonov <eugeni.dodonov at intel.com>
> > Date:   Wed Feb 8 12:53:50 2012 -0800
> > 
> >     drm/i915: gen7: Implement an L3 caching workaround.
> > 
> > the L3 cache aging was disabled. This was part of a shotgun response
> > to a number of GPU hang bugs, but there appears to be no documentation
> > to suggest that disabling the L3 cache age was ever required (to prevent
> > the GPU hangs).
> 
> Bspec still lists the 0xF value in the w/a list, but the actual register
> description doesn't say that this bit needs to be set. All the other
> bits match either the default values, or specific notes about which bits
> need to be set.
> 
> So I get the feeling this should be fine:
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch