[Intel-gfx] [PATCH v2 00/21] drm/i915: vlv power domains support

Imre Deak imre.deak at intel.com
Tue Mar 4 18:22:49 CET 2014


See the v1 cover letter for a description.

In v2:
- addressed all the review comments (hopefully) from Ville, Jesse, Paulo
  and Chris
- added back the power_well->always_on flag, we need it for state
  tracking
- fixed locking around valleyview_{enable,disable}_display_irqs
- Added back intel_runtime_pm_get/put() to the DP detect handler, we can't
  remove it before corresponding intel_runtime_pm_get/put() calls are
  added to the HSW/BDW power well enable/disable handlers. We can do
  this after Paulo's 'Merge PC8 with runtime PM, v2' patchset.
- added Jesse's r-bs where granted

Note that this can be applied independently of Paulo's 'Runtime PM
fixes' and 'Merge PC8 with runtime PM, v2' patchsets. They have only
trivial conflicts where one patch is adding RPM get/put and the other
power domain get/put calls.

Imre Deak (21):
  drm/i915: use drm_i915_private everywhere in the power domain api
  drm/i915: fold in __intel_power_well_get/put functions
  drm/i915: move modeset_update_power_wells earlier
  drm/i915: move power domain macros to intel_pm.c
  drm/i915: add init power domain to always-on power wells
  drm/i915: split power well 'set' handler to separate
    enable/disable/sync_hw
  drm/i915: add noop power well handlers instead of NULL checking them
  drm/i915: add port power domains
  drm/i915: get port power domain in connector detect handlers
  drm/i915: check port power domain when reading the encoder hw state
  drm/i915: check pipe power domain when reading its hw state
  drm/i915: vlv: keep first level vblank IRQs masked
  drm/i915: sanitize PUNIT register macro definitions
  drm/i915: factor out reset_vblank_counter
  drm/i915: switch order of power domain init wrt. irq install
  drm/i915: use power domain api to check vga power state
  drm/i915: sanity check power well sw state against hw state
  drm/i915: vlv: factor out valleyview_display_irq_install
  drm/i915: move hsw power domain comment to its right place
  drm/i915: factor out intel_set_cpu_fifo_underrun_reporting_nolock
  drm/i915: power domains: add vlv power wells

 drivers/gpu/drm/i915/i915_debugfs.c  |  22 ++
 drivers/gpu/drm/i915/i915_dma.c      |  16 +-
 drivers/gpu/drm/i915/i915_drv.c      |   4 +-
 drivers/gpu/drm/i915/i915_drv.h      |  64 +++--
 drivers/gpu/drm/i915/i915_irq.c      | 144 ++++++++---
 drivers/gpu/drm/i915/i915_reg.h      |  28 ++-
 drivers/gpu/drm/i915/intel_crt.c     |  42 +++-
 drivers/gpu/drm/i915/intel_ddi.c     |   2 +-
 drivers/gpu/drm/i915/intel_display.c | 255 ++++++++++++-------
 drivers/gpu/drm/i915/intel_dp.c      |  25 ++
 drivers/gpu/drm/i915/intel_drv.h     |  22 +-
 drivers/gpu/drm/i915/intel_dsi.c     |  13 +-
 drivers/gpu/drm/i915/intel_hdmi.c    |  29 ++-
 drivers/gpu/drm/i915/intel_pm.c      | 460 +++++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_uncore.c  |   4 +-
 15 files changed, 883 insertions(+), 247 deletions(-)

-- 
1.8.4




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