[Intel-gfx] [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions

[Daniel Vetter]

On Wed, Mar 05, 2014 at 02:40:58PM +0000, Damien Lespiau wrote:
> On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > We have two names for the same register CHICKEN_PIPESL_1 and
> > HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one.
> > 
> > Also rename the FBCQ disable bit to resemble the name we've
> > given to a similar bit on earlier platforms.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch