[Intel-gfx] [PATCH] drm/i915: Fail gpu reset if the forcewake fifo hasn't drained

Daniel Vetter daniel at ffwll.ch
Sat Mar 8 20:58:24 CET 2014

On Sat, Mar 8, 2014 at 7:50 PM, Ben Widawsky <ben at bwidawsk.net> wrote:
> I've seen this too. Though I think the WARN does coincide with what the
> docs state - it doesn't seem to match reality. So I totally agree this
> is the right course.
> However, for my curiosity, Chris, can you elaborate on why you think it
> doesn't make sense?

Our current fifo code would be broken - we stall for the fifo entries
to refill if the value drops below NUM_FIFO_ENTRIES_RESERVED. Hence if
the register value is zero right after reset, something is terribly
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

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