[Intel-gfx] [PATCH v2 2/3] drm/i915: wait for rings to become idle once disabled

[Chris Wilson]

On Wed, Mar 12, 2014 at 04:39:41PM +0530, naresh.kumar.kachhi at intel.com wrote:
> From: Naresh Kumar Kachhi <naresh.kumar.kachhi at intel.com>
> 
> make sure we wait for rings to become idle once they are
> disabled. In case of timeout print an error message
> 
> Signed-off-by: Naresh Kumar Kachhi <naresh.kumar.kachhi at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 2 ++
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++
>  3 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 146609a..6174fda 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -748,6 +748,7 @@ enum punit_power_well {
>  #define RING_INSTPS(base)	((base)+0x70)
>  #define RING_DMA_FADD(base)	((base)+0x78)
>  #define RING_INSTPM(base)	((base)+0xc0)
> +#define RING_MI_MODE(base)	((base)+0x9c)
>  #define INSTPS		0x02070 /* 965+ only */
>  #define INSTDONE1	0x0207c /* 965+ only */
>  #define ACTHD_I965	0x02074
> @@ -824,6 +825,7 @@ enum punit_power_well {
>  # define VS_TIMER_DISPATCH				(1 << 6)
>  # define MI_FLUSH_ENABLE				(1 << 12)
>  # define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
> +# define MODE_IDLE					(1 << 9)
>  
>  #define GEN6_GT_MODE	0x20d0
>  #define GEN7_GT_MODE	0x7008
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 42b4001..4da2211 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -445,6 +445,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
>  	I915_WRITE_HEAD(ring, 0);
>  	ring->write_tail(ring, 0);
>  
> +	/* Wait for idle */
This comment is too close to "i++; /* post-increment the variable i */"
Personally, I would remove the newline here so that this adjoins the
/* Stop the rings if it's running */ block, then that comment would seem
to naturally apply.

> +	if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
> +		/* don't fail here, log a message to keep track */
> +		DRM_ERROR("%s :timed out trying to stop ring", ring->name);

Missed the trailing '\n'.

> +
>  	if (I915_NEED_GFX_HWS(dev))
>  		intel_ring_setup_status_page(ring);
>  	else
> @@ -982,6 +987,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
>  	/* Flush the TLB for this page */
>  	if (INTEL_INFO(dev)->gen >= 6) {
>  		u32 reg = RING_INSTPM(ring->mmio_base);
> +

Spurious whitespace change.

>  		I915_WRITE(reg,
>  			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
>  					      INSTPM_SYNC_FLUSH));
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 09af920..f11ceb2 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -33,6 +33,8 @@ struct  intel_hw_status_page {
>  #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
>  #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
>  
> +#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
> +
>  enum intel_ring_hangcheck_action {
>  	HANGCHECK_IDLE = 0,
>  	HANGCHECK_WAIT,
> -- 
> 1.8.5.3
> 
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-- 
Chris Wilson, Intel Open Source Technology Centre