[Intel-gfx] [PATCH 09/20] drm/i915: fix SERR_INT init/reset code

[Ben Widawsky]

On Fri, Mar 07, 2014 at 08:10:25PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> The SERR_INT register is very similar to the other IIR registers, so
> let's zero it at preinstall/uninstall and WARN for a non-zero value at
> postinstall, just like we do with the other IIR registers. For this
> one, there's no need to double-clear since it can't store more than
> one interrupt.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Without the assert that I don't like, this is
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4d0a8b1..d295624 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2811,6 +2811,10 @@ static void ibx_irq_preinstall(struct drm_device *dev)
>  		return;
>  
>  	GEN5_IRQ_RESET(SDE);
> +
> +	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
> +		I915_WRITE(SERR_INT, 0xffffffff);
> +
>  	/*
>  	 * SDEIER is also touched by the interrupt handler to work around missed
>  	 * PCH interrupts. Hence we can't update it after the interrupt handler
> @@ -2949,7 +2953,7 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>  	} else {
>  		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
>  
> -		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
> +		GEN5_ASSERT_IIR_IS_ZERO(SERR_INT);
>  	}
>  
>  	GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
> @@ -3303,7 +3307,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
>  
>  	GEN5_IRQ_RESET(SDE);
>  	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
> -		I915_WRITE(SERR_INT, I915_READ(SERR_INT));
> +		I915_WRITE(SERR_INT, 0xffffffff);
>  }
>  
>  static void i8xx_irq_preinstall(struct drm_device * dev)
> -- 
> 1.8.5.3
> 
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-- 
Ben Widawsky, Intel Open Source Technology Center