[Intel-gfx] [PATCH 20/20] drm/i915: add POSTING_READs to the IRQ init/reset macros

[Ben Widawsky]

On Fri, Mar 07, 2014 at 08:10:36PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> I previously chose to keep the POSTING_READ calls as something to be
> done by the macro callers, but the conclusion after discussing this on
> the mailing list is that leaving the POSTING_READ calls to the macros
> makes the code safer, and the additional useless register reads
> shouldn't be noticeable. So move the POSTING_READ calls to the
> callers.

Can you just squash this into the earlier patch? Either way, 
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 16 +++++-----------
>  1 file changed, 5 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 79a8196..dee3a3b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -80,11 +80,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
>  	[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
>  };
>  
> -/*
> - * IIR can theoretically queue up two events. Be paranoid.
> - * Also, make sure callers of these macros have something equivalent to a
> - * POSTING_READ on the IIR register.
> - * */
> +/* IIR can theoretically queue up two events. Be paranoid. */
>  #define GEN8_IRQ_RESET_NDX(type, which) do { \
>  	I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
>  	POSTING_READ(GEN8_##type##_IMR(which)); \
> @@ -92,6 +88,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
>  	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
>  	POSTING_READ(GEN8_##type##_IIR(which)); \
>  	I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
> +	POSTING_READ(GEN8_##type##_IIR(which)); \
>  } while (0)
>  
>  #define GEN5_IRQ_RESET(type) do { \
> @@ -101,6 +98,7 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
>  	I915_WRITE(type##IIR, 0xffffffff); \
>  	POSTING_READ(type##IIR); \
>  	I915_WRITE(type##IIR, 0xffffffff); \
> +	POSTING_READ(type##IIR); \
>  } while (0)
>  
>  /*
> @@ -117,12 +115,14 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
>  	GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
>  	I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
>  	I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
> +	POSTING_READ(GEN8_##type##_IER(which)); \
>  } while (0)
>  
>  #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
>  	GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
>  	I915_WRITE(type##IMR, (imr_val)); \
>  	I915_WRITE(type##IER, (ier_val)); \
> +	POSTING_READ(type##IER); \
>  } while (0)
>  
>  /* For display hotplug interrupt */
> @@ -2843,7 +2843,6 @@ static void gen5_gt_irq_reset(struct drm_device *dev)
>  	GEN5_IRQ_RESET(GT);
>  	if (INTEL_INFO(dev)->gen >= 6)
>  		GEN5_IRQ_RESET(GEN6_PM);
> -	POSTING_READ(GTIIR);
>  }
>  
>  /* drm_dma.h hooks
> @@ -2917,7 +2916,6 @@ static void gen8_irq_reset(struct drm_device *dev)
>  	GEN5_IRQ_RESET(GEN8_DE_PORT_);
>  	GEN5_IRQ_RESET(GEN8_DE_MISC_);
>  	GEN5_IRQ_RESET(GEN8_PCU_);
> -	POSTING_READ(GEN8_PCU_IIR);
>  
>  	ibx_irq_reset(dev);
>  }
> @@ -3016,7 +3014,6 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
>  		dev_priv->pm_irq_mask = 0xffffffff;
>  		GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
>  	}
> -	POSTING_READ(GTIER);
>  }
>  
>  static int ironlake_irq_postinstall(struct drm_device *dev)
> @@ -3213,7 +3210,6 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
>  
>  	for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
>  		GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
> -	POSTING_READ(GEN8_GT_IER(0));
>  }
>  
>  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> @@ -3232,10 +3228,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	for_each_pipe(pipe)
>  		GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
>  				  de_pipe_enables);
> -	POSTING_READ(GEN8_DE_PIPE_ISR(0));
>  
>  	GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
> -	POSTING_READ(GEN8_DE_PORT_IER);
>  }
>  
>  static int gen8_irq_postinstall(struct drm_device *dev)
> -- 
> 1.8.5.3
> 
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-- 
Ben Widawsky, Intel Open Source Technology Center