[Intel-gfx] [PATCH v2 1/3] drm/i915/vlv: Added a rendering specific Hw WA 'WaTlbInvalidateStoreDataBefore'

[Gupta, Sourab]

On Fri, 2014-02-07 at 12:22 +0000, Goel, Akash wrote:
> From: Akash Goel <akash.goel at intel.com>
> 
> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
> Store data commands.
> 
> v2: Modified the WA comment. (Ville)
> 
> Signed-off-by: Akash Goel <akash.goel at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d897a19..2ac6600 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2183,6 +2183,29 @@ intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
>         uint32_t flush_domains;
>         int ret;
> 
> +       if (IS_VALLEYVIEW(ring->dev)) {
> +               /*
> +                * WaTlbInvalidateStoreDataBefore
> +                * Before pipecontrol with TLB invalidate set, need 2 store
> +                * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX)
> +                * Without this, hardware cannot guarantee the command after the
> +                * PIPE_CONTROL with TLB inv will not use the old TLB values.
> +                * FIXME, should also apply to snb, ivb
> +                */
> +               int i;
> +               ret = intel_ring_begin(ring, 4 * 2);
> +               if (ret)
> +                       return ret;
> +               for (i = 0; i < 2; i++) {
> +                       intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
> +                       intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX <<
> +                                               MI_STORE_DWORD_INDEX_SHIFT);
> +                       intel_ring_emit(ring, 0);
> +                       intel_ring_emit(ring, MI_NOOP);
> +               }
> +               intel_ring_advance(ring);
> +       }
> +
>         flush_domains = 0;
>         if (ring->gpu_caches_dirty)
>                 flush_domains = I915_GEM_GPU_DOMAINS;
> --
> 1.8.5.2
> 
Hi Ville,

Can you please let us know the status of this patch, as there are no
further comments to address here.

Regards,
Sourab