[Intel-gfx] [PATCH 2/2] drm/i915/vlv: Enabling the TLB invalidate bit in GFX Mode register
chris at chris-wilson.co.uk
Fri Mar 21 14:17:53 CET 2014
On Fri, Mar 21, 2014 at 01:09:12PM +0000, Gupta, Sourab wrote:
> On Fri, 2014-03-21 at 12:58 +0000, Chris Wilson wrote:
> > On Fri, Mar 21, 2014 at 06:05:04PM +0530, sourab.gupta at intel.com wrote:
> > > From: Akash Goel <akash.goel at intel.com>
> > >
> > > This patch Enables the bit for TLB invalidate in GFX Mode register.
> > >
> > > According to bspec, When enabled this bit limits the invalidation
> > > of the TLB only to batch buffer boundaries, to pipe_control
> > > commands which have the TLB invalidation bit set and sync flushes.
> > > If disabled, the TLB caches are flushed for every full flush of
> > > the pipeline.
> > So why do we want to not disable it?
> > -Chris
> Hi Chris,
> As per the description, enabling this bit will make the TLB invalidation
> more optimal. Otherwise, TLB invalidation will happen for every full
> pipeline flush. Thats why we are enabling this bit.
You are not enabling the bit either, you simply do not disable it.
Chris Wilson, Intel Open Source Technology Centre
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