[Intel-gfx] [PATCH 09/12] drm/i915: Don't clobber CHICKEN_PIPESL_1 on BDW

[Ben Widawsky]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Misplaced parens cause us to totally clobber the CHICKEN_PIPESL_1
registers with 0xffffffff. Move the parens to the correct place
to avoid this.

In particular this caused bit 30 of said registers to be set, which
caused the sprite CSC to produce incorrect results.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72220
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
[BDW 3.14 backport]
Cc: stable at vger.kernel.org
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

Conflicts:
	drivers/gpu/drm/i915/intel_pm.c
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2b82a6b..f9a63b7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4745,8 +4745,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
 	/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
 	for_each_pipe(i) {
 		I915_WRITE(CHICKEN_PIPESL_1(i),
-			   I915_READ(CHICKEN_PIPESL_1(i) |
-				     DPRS_MASK_VBLANK_SRD));
+			   I915_READ(CHICKEN_PIPESL_1(i)) |
+			   DPRS_MASK_VBLANK_SRD);
 	}
 
 	/* Use Force Non-Coherent whenever executing a 3D context. This is a
-- 
1.9.1