[Intel-gfx] [PATCH 2/3] drm/i915: Use RMW to update chicken bits in gen7_enable_fbc()

[Ben Widawsky]

On Wed, Mar 05, 2014 at 01:05:46PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> gen7_enable_fbc() may write to some registers which we've already
> touched, so use RMW so that we don't undo any previous updates.
> 
> Also note that we implemnt WaFbcAsynchFlipDisableFbcQueue:bdw.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

CC stable?

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 245d3ae..3411ad7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -294,10 +294,13 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
>  
>  	if (IS_IVYBRIDGE(dev)) {
>  		/* WaFbcAsynchFlipDisableFbcQueue:ivb */
> -		I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
> +		I915_WRITE(ILK_DISPLAY_CHICKEN1,
> +			   I915_READ(ILK_DISPLAY_CHICKEN1) |
> +			   ILK_FBCQ_DIS);
>  	} else {
> -		/* WaFbcAsynchFlipDisableFbcQueue:hsw */
> +		/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
>  		I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
> +			   I915_READ(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe)) |
>  			   HSW_BYPASS_FBC_QUEUE);
>  	}
>  
> -- 
> 1.8.3.2
> 
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-- 
Ben Widawsky, Intel Open Source Technology Center