[Intel-gfx] [PATCH v2] drm/i915/vlv: Enabling the TLB invalidate bit in GFX Mode register

[Chris Wilson]

On Sat, Mar 22, 2014 at 04:25:31AM +0000, Gupta, Sourab wrote:
> On Fri, 2014-03-21 at 16:52 +0000, Chris Wilson wrote:
> > On Fri, Mar 21, 2014 at 08:58:08PM +0530, sourab.gupta at intel.com wrote:
> > > From: Akash Goel <akash.goel at intel.com>
> > > 
> > > This patch Enables the bit for TLB invalidate in GFX Mode register.
> > > 
> > > According to bspec,  When enabled this bit limits the invalidation
> > > of the TLB only to batch buffer boundaries, to pipe_control
> > > commands which have the TLB invalidation bit set and sync flushes.
> > > If disabled, the TLB caches are flushed for every full flush of
> > > the pipeline.
> > > 
> > > v2: Explicitly enabling TLB invalidate bit instead of assuming
> > > default 1 (Chris Wilson)
> > 
> > Right, but there is nothing special about this code for vlv, all of gen7
> > share the same TLB invalidation code, and there is no documented reason
> > not to do the switch. So do a cursory test on ivb/hsw and send a patch
> > that doesn't say FIXME.
> > -Chris
> > 
> Hi Chris,
> I agree, this could be applicable to ivb also. But we are constrained by
> the availability of ivb/hsw machines and we're not able to test it on
> those. We didn't want to cause any regression on those platforms. Thats
> why we were limiting our patch to vlv only with a FIXME comment. We've
> done this for other WAs also.
> 
> If required we can put this patch for full GEN7 (not tested on ivb/hsw)
> and keep our fingers crossed! :)

How about for the generalised patch,
Tested-by: Chris Wilson <chris at chris-wilson.co.uk> # ivb, hsw

Happy now? :)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre